Glitch warnings in Modelsim with Lattice ispLever 7.0

Started by Sbreheny in comp.arch.fpga13 years ago

Hi all, I'm having trouble trying to figure out why this VHDL synthesizes to something which generates glitches when post-route simulated...

Hi all, I'm having trouble trying to figure out why this VHDL synthesizes to something which generates glitches when post-route simulated in Modelsim. Regardless of what I do, I always get tons of warnings from VitalGlitch in Modelsim about glitches on slices involving "count". I am using Precision to synthesize. These tools are all part of Lattice ispLever v7.0. The clock is 1MHz. This...


Bidirectional Bus problem with ModelSim.

Started by Telenochek in comp.arch.fpga16 years ago 3 replies

Hello everyone! I am having a problem in ModelSim XE 5.8c with a very simple bidirectional bus. ModelSim outputs a bunch of XXXX's where its...

Hello everyone! I am having a problem in ModelSim XE 5.8c with a very simple bidirectional bus. ModelSim outputs a bunch of XXXX's where its supposed to output data. I am using test bench waveforms with Xilinx ISE 6.303i. Basically there are only 3 signals: the bidir. bus, wr_enable and clk. The idea behind this simple code is: if WR_EN is HIGH -> store bus data into a flip-flop on next c


ModelSim

Started by Brad Smallridge in comp.arch.fpga17 years ago 9 replies

Where are there some really easy point and click tutorials for ModelSIM?

Where are there some really easy point and click tutorials for ModelSIM?


ModelSim 6.0 v 5.7 Can't read file

Started by Brad Smallridge in comp.arch.fpga15 years ago 3 replies

When I upgrade(?) to ISE 7.1.4 and ModelSim 6.0 I find my testbenches can not read binary files. Is this a technical problem or a downgrade on...

When I upgrade(?) to ISE 7.1.4 and ModelSim 6.0 I find my testbenches can not read binary files. Is this a technical problem or a downgrade on ModelSIM XE free offering. Note this is a binary file read not a textio file read which, according to the manual, is still available. Brad Smallridge Ai Vision


SystemVerilog Verification Example using Quartus and ModelSim

Started by jjli...@hotmail.com in comp.arch.fpga11 years ago 16 replies

Hello, I've been using the Quartus Simulator for many years and have recently started learning about the SystemVerilog Verification. I...

Hello, I've been using the Quartus Simulator for many years and have recently started learning about the SystemVerilog Verification. I was hoping to find someone that has done this and is using Quartus. I am new to ModelSim and I configure Quartus to launch ModelSim to run my simulation. If anyone could provide a simple example of a program and a Verification testbench I would very much appre...


Xilinx Modelsim XE-III 6.2g no more Systemverilog support?

Started by Xilinx User in comp.arch.fpga14 years ago 4 replies

I upgraded my Modelsim XE-III 6.2c starter edition to Modelsm XE-III 6.2g starter edition. Before isntalling the new software, I uninstalled...

I upgraded my Modelsim XE-III 6.2c starter edition to Modelsm XE-III 6.2g starter edition. Before isntalling the new software, I uninstalled 6.2c (from Control Panel), and then I deleted the \modelsim_xe_starter directory on my hard-drive. After the upgrade, I recycled the license.dat file from the old modelsim starter edition. (The license checker says it's valid.) I tried running some ...


Condition Coverage Using ModelSim

Started by arvi in comp.arch.fpga16 years ago

When I use a function that returns a boolean in a 'If' condition, ModelSim reports that "Condition Coverage ignoring this condition". Is it a...

When I use a function that returns a boolean in a 'If' condition, ModelSim reports that "Condition Coverage ignoring this condition". Is it a limitation in ModelSim?


Why does modelsim always look for another simulation model?

Started by fl in comp.arch.fpga15 years ago

Hi, I am learning Modelsim (6.1e) along with ISE webpack. I had done a behavior simulation, then a post-translate simulation. Now, I go back to...

Hi, I am learning Modelsim (6.1e) along with ISE webpack. I had done a behavior simulation, then a post-translate simulation. Now, I go back to do the behavioral simulation again. When I am in Modelsim, I modify the source vhdl code after I terminate the simulation. I recompile it. Then I simulate the testbench file. I find that the simulation is on the post-translation, not the behavioral s...


xilinx beginner modelsim question

Started by Zorjak in comp.arch.fpga13 years ago 4 replies

Hi!!! I started recently with the xilinx software and these days I am trying to become more familiar with the modelsim and ise. I wanted to...

Hi!!! I started recently with the xilinx software and these days I am trying to become more familiar with the modelsim and ise. I wanted to test some basic counter simulation in modelsim so I used this simple code counter design file library ieee ; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is port( clk: in std_logic; reset: in...


problems with using altera vhdl testbench in ModelSim

Started by Anonymous in comp.arch.fpga14 years ago 3 replies

Hi all, I try to convert a file with extension *.vwf (used in Quartus) to btim or tim one. I tried to use exported (Quartus option) to vht...

Hi all, I try to convert a file with extension *.vwf (used in Quartus) to btim or tim one. I tried to use exported (Quartus option) to vht (vhd) format files in ModelSim Actel Customer version but with no success. Could you tell me why ModelSim (Libero Design Flow) doesn't see the testbench file created in that way (there is'nt any altera libraries in the code) and propose any solution? ...


ModelSim vsim-3601 message

Started by Jaime Andres Aranguren Cardona in comp.arch.fpga15 years ago 3 replies

Good day, I am trying to simulate a design for an Spartan3-200, on Webpack 7.1i SP4 with ModelSim XE III/Starter 6.0a. The design...

Good day, I am trying to simulate a design for an Spartan3-200, on Webpack 7.1i SP4 with ModelSim XE III/Starter 6.0a. The design simulates perfectly for a functional simulation, running own .do file on ModelSim. However, if I run the same .do file on the simulation model generated with the "Generate Post-Synthesis Simulation Model" process, I get the following messages (several t...


Modelsim SE 6.2c trying to use Xilinx ISE 9.1i simulation libraries... not working.

Started by Tony Thai in comp.arch.fpga14 years ago 3 replies

Hi All, Hopefully this is a simple fix... I complied Xilinx simulation libraries with COMPXLIB... and it seemed to worked fine. The...

Hi All, Hopefully this is a simple fix... I complied Xilinx simulation libraries with COMPXLIB... and it seemed to worked fine. The modelsim.ini was changed to point to the new libraries. I checked ModelSim to see if xilinx libraries were in the library window (panel/tab), and they were as expected. When I start to compile my design, I see this message (not warning or error): # Ref...


The simulation library compilation wizard of EDK can't find modelsim

Started by Rebecca in comp.arch.fpga14 years ago

Hi, All: When I complie the simulation library in EDK 9.1.01i using the library compilation wizard, it told me that "modlesim is not found!...

Hi, All: When I complie the simulation library in EDK 9.1.01i using the library compilation wizard, it told me that "modlesim is not found! please ensure that the simulator is correctly installed and/or the necessary envoroment settings are available". But I do have modelsim se 6.2e and 6.1e intalled on my machine and they work fine. The only system variable I set for modelsim is LM_LICENSE_...


The simulation library compilation wizard of EDK can't find modelsim

Started by Rebecca in comp.arch.fpga14 years ago 3 replies

Hi, All: When I complie the simulation library in EDK 9.1.01i using the library compilation wizard, it told me that "modlesim is not found!...

Hi, All: When I complie the simulation library in EDK 9.1.01i using the library compilation wizard, it told me that "modlesim is not found! please ensure that the simulator is correctly installed and/or the necessary envoroment settings are available". But I do have modelsim se 6.2e and 6.1e intalled on my machine and they work fine. The only system variable I set for modelsim is LM_LICENSE_...


ModelSim SE PLUS 6.1B. Problem to simulate RocketIO in GT_CUSTOM mode

Started by Anonymous in comp.arch.fpga15 years ago 3 replies

Modelsim report is: # Reading C:/Modeltech_6.1b/tcl/vsim/pref.tcl # // ModelSim SE 6.1b Sep 8 2005 # // # // Copyright Mentor Graphics...

Modelsim report is: # Reading C:/Modeltech_6.1b/tcl/vsim/pref.tcl # // ModelSim SE 6.1b Sep 8 2005 # // # // Copyright Mentor Graphics Corporation 2005 # // All Rights Reserved. # // # // THIS WORK CONTAINS TRADE SECRET AND # // PROPRIETARY INFORMATION WHICH IS THE PROPERTY # // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS # // AND IS SUBJECT TO LICENSE TERMS. #...


problem in simulating FFT core on ISE 7.1

Started by tamania in comp.arch.fpga15 years ago 1 reply

hi im using xilinx ISE 7.1i with modelsim XE 6.0 starter in verilog....i have been trying to simulate FFT core on modelsim...also i...

hi im using xilinx ISE 7.1i with modelsim XE 6.0 starter in verilog....i have been trying to simulate FFT core on modelsim...also i have downloaded "radix 2 fft core" from xilinx core generator examples on xilinx site but failed to simulate it.the error msg in modelsim is as under... ------------------------------------------------------------------------------------------------ ---------


Altera SOPC ModelSim question

Started by Martin Schoeberl in comp.arch.fpga15 years ago 2 replies

I'm trying to construct a SOPC component of JOP [1]. As it did not work in the FPGA on the first try (of course) I would like to simulate it...

I'm trying to construct a SOPC component of JOP [1]. As it did not work in the FPGA on the first try (of course) I would like to simulate it with ModelSim (Altera version). However, when I start ModelSim from Quartus I get following error: # ** Error: (vcom-11) Could not find C:\altera\Modeltech_ae\win32aloem/../altera/vhdl/altera.altera_europa_support_lib. # ** Error: D:/usr/cpu/jop/qu...


ModelSim # Error loading design

Started by mBird in comp.arch.fpga15 years ago 6 replies

I just downloaded Xilinx ISE 8.1 and ModelSim XE III/Starter 6.0d I make a simple project, using schematic (one and gate) an dthen make a test...

I just downloaded Xilinx ISE 8.1 and ModelSim XE III/Starter 6.0d I make a simple project, using schematic (one and gate) an dthen make a test bench waveform. I then do Simulate Behaviural Model but no matter what I do I always get # Error loading design with no other indication of erors. In the previous version of ISE and ModelSim it all worked so I am not sure what is error? Any help g...


MicroBlaze Simulation Question

Started by jazzy_21 in comp.arch.fpga10 years ago

Hallo! I'm only starting with Xilinx EDK, so i'm sorry for my probably stupid question. Also my english is not a perfect. The problem is: I use...

Hallo! I'm only starting with Xilinx EDK, so i'm sorry for my probably stupid question. Also my english is not a perfect. The problem is: I use Xilinx EDK 10.1 and ModelSim SE 6.3d. I made a simple project (led blink) with Microblaze and try to do behavioral simulation from EDK (I have compiled sim libraries, generate simulation files and run ModelSim). But when I run the simulation in Modelsim i...


ModelSim XE and WindowsXP

Started by Nemesis in comp.arch.fpga16 years ago 8 replies

Hi all, I'm trying to install ModelSim XE (both II and III) on a WindowsXP box but I can't get it working when I login as a simple no privileged...

Hi all, I'm trying to install ModelSim XE (both II and III) on a WindowsXP box but I can't get it working when I login as a simple no privileged User. I installed the software logged as Administrator, and I loaded the license.dat file, in this situation the software works correctly, but when I use the computer as a normal User (I'm not the Administrator of that computer) ModelSim doesn't w...