Timing Simulation ModelSim / Quartus

Started by Cornel Arnet in comp.arch.fpga17 years ago 2 replies

Hi there, I want to perform a timing simulation with ModelSim SE5.7e from the output generated by Quartus II 3.0. So, I add "mydesign.vho" to...

Hi there, I want to perform a timing simulation with ModelSim SE5.7e from the output generated by Quartus II 3.0. So, I add "mydesign.vho" to my modelsim project and it compiles without any errors or warnings. However, when I try to load the design for simulation (without *.sdo for now) the following is printed out: # Compile of mydesign.vho was successful. vsim work.mydesign(structure...


modelsim and rocketio

Started by shalini in comp.arch.fpga17 years ago 2 replies

When doing behavioral simulation using modelsim 5.8b SE version for rocket io i am getting the warning as # No default binding for component...

When doing behavioral simulation using modelsim 5.8b SE version for rocket io i am getting the warning as # No default binding for component 'gt_fibre_channel_4'(no entity gt_fibre_channel) was found. and all the outputs of mgt are having the value 'U'.


Aldec ActiveHDL vs. ModelSim

Started by Anonymous in comp.arch.fpga14 years ago 1 reply

I currently use Altera Quartus along with ModelSim for FPGA designs using Verilog. In ModelSim I use the "$random" term to create a random...

I currently use Altera Quartus along with ModelSim for FPGA designs using Verilog. In ModelSim I use the "$random" term to create a random driver. My company is considering updating its tools so that we can get code coverage capabilities and possibly automatically generate block diagrams from the Verilog code. I've looked into Aldec ActiveHDL and it seems like most of this software provide...


How to save a changed *.wlf file with ModelSim

Started by Weng Tianxiang in comp.arch.fpga14 years ago 3 replies

Hi, Our hardware engineer got *.vcd file from Xilinx ChipScope, then I swithced the *.vcd file to *.wlf file in ModelSim using vcd2wlf command....

Hi, Our hardware engineer got *.vcd file from Xilinx ChipScope, then I swithced the *.vcd file to *.wlf file in ModelSim using vcd2wlf command. After getting *.wlf file, I combined a lot of signals, added color, changed their display format and so on. After that I would like to save the file for later use. But I couldn't find any appropriate tools in ModelSim to save the *.wlf file. The o...


Modelsim crash (code 211) when using library

Started by Doug Miller in comp.arch.fpga17 years ago 1 reply

I am using a library prepared for testbenching a future core by a core vendor. In some simulations, the library works fine, but in others...

I am using a library prepared for testbenching a future core by a core vendor. In some simulations, the library works fine, but in others it causes Modelsim to crash during a vsim. When it crashes, it gives a code of 211 which is a segmentation fault. The crash is total - Modelsim exits immediately, printing a stack trace to its stderr, but nothing to its main console. I believe the cra...


Memory Initialization Files in Modelsim

Started by ALuPin in comp.arch.fpga17 years ago 6 replies

Dear Sir or Madam, I want to simulate a VHDL design. It includes RAM structures with .mif files (memory initialization files in...

Dear Sir or Madam, I want to simulate a VHDL design. It includes RAM structures with .mif files (memory initialization files in QuartusII). Modelsim seems not to support that kind of files. So I use .hex files. In QuartusII they can be included in the MegaWizard- PlugInManager. But how do I involve these .hex files when simulating in Modelsim? Do they have to be compiled additional...


Question on ModelSim wave viewer

Started by Gabor in comp.arch.fpga13 years ago 3 replies

I often look through waveform views with many screens worth of signals, so I like to re-arrange the signals to have those of interest at...

I often look through waveform views with many screens worth of signals, so I like to re-arrange the signals to have those of interest at the top of the view. With ModelSim PE 5.7, I could find the signals I wanted, select them, then cut (Ctrl+X), go to the top of the window (Ctrl +Home) and paste (Ctrl+V) these signals at the top of the window. Now with ModelSim 6.3, I find that this tr...


Simulation error

Started by flipoo in comp.arch.fpga11 years ago 1 reply

Hi guys, When i try to simulate a simple EXOR i get the following error: # ** Warning: A ModelSim starter license was detected and will be...

Hi guys, When i try to simulate a simple EXOR i get the following error: # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Licensing checkout error with feature xe-starter. (Error code -9.) # The hostid of the license does not match the hostid ...


Internal Signals and other questions with ModelSim XE/II Starter 5.7g VHDL Testbench

Started by Martin Maurer in comp.arch.fpga17 years ago 2 replies

Hello, i am trying to learn how to use ModelSim with a VHDL Testbench, but i don't find any answers on a few of my answers. At the moment i...

Hello, i am trying to learn how to use ModelSim with a VHDL Testbench, but i don't find any answers on a few of my answers. At the moment i start ModelSim always via "Simulate Post-Translate VHDL" from Xilinx Project Navigator. 1) I can see all my stimuli, which are mainly the external in- and outputs. They seems to toggle fine. But how can i display the internal signals ? Is the only s...


Modelsim

Started by maxascent in comp.arch.fpga15 years ago 3 replies

Hi Does has anyone experienced problems with modelsim running slowly? I am not talking about simulation speed but rather when I have signals...

Hi Does has anyone experienced problems with modelsim running slowly? I am not talking about simulation speed but rather when I have signals open in the wave window. There is a delay with zooming in and scrolling before it actually happens. Its not like I have a slow pc either. Cheers Jon


New modelsim PE student edition 6.2g and Xilinx ISE 9.1i User Linking problems

Started by Anonymous in comp.arch.fpga14 years ago 3 replies

I am using these programs in my digital class but do not know how to link modelsim to ISE. In our school lab, after I make my schematic, I can...

I am using these programs in my digital class but do not know how to link modelsim to ISE. In our school lab, after I make my schematic, I can run model sim to simulate it from inside ISE. Does someone know how I would set this up?


ModelSim fails to connect my project components

Started by kadhiem_ayob in comp.arch.fpga12 years ago 1 reply

I am trying to simulate in Modelsim XE web edition a verilog only project consisting of top level and few components. All components have same...

I am trying to simulate in Modelsim XE web edition a verilog only project consisting of top level and few components. All components have same time resolution units and have wire type outputs. The problem is that Modelsim doesn't recognise the drive of any component's output connected to another's input. Yet it accepts the drive when connected to an output at toplevel itself. What am I missing he...


Stratix - Virtex2Pro Co-Simulation using modelsim !

Started by Adarsh Kumar Jain in comp.arch.fpga17 years ago

Hi, I am trying to simulate together a Stratix and a V2Pro design using ModelSim. Both the designs simulate correctly individually. I use the...

Hi, I am trying to simulate together a Stratix and a V2Pro design using ModelSim. Both the designs simulate correctly individually. I use the Rocket IOs in the V2Pros so have set the modelsim.ini file correctly. The interesting thing is that in the co-simulation, all parts of the design are ok except the Rocket IO part which makes me think that it is probably due to the Smartmodel interfa...


ModelSim view internal signals in instantiated verilog modules

Started by melinda in comp.arch.fpga12 years ago 9 replies

Hi all, I am simulating a entity with Modelsim (v6.5c). Modelsim only displays the input/output signals of the simulated top entity. When I...

Hi all, I am simulating a entity with Modelsim (v6.5c). Modelsim only displays the input/output signals of the simulated top entity. When I run simulation Modelsim displays only changes of input/output signals of the top entity verilog module i.e. testbench (in objects window i.e. in wave window), but nothing happening with signals declared in the instantiated verilog modules. (PS: In Cad...


How to change the font size in text editor of modelsim

Started by fl in comp.arch.fpga15 years ago 1 reply

Hi, I am using Modelsim 6.2e with the Xilinx webpack 8.2. When I print the vhdl text from the text editor of Modelsim, the font size is very...

Hi, I am using Modelsim 6.2e with the Xilinx webpack 8.2. When I print the vhdl text from the text editor of Modelsim, the font size is very big. How to modify the font size in the printed paper? I do not find such dialogue box. Thank you very much.


How to change the font size in text editor of modelsim

Started by fl in comp.arch.fpga15 years ago

Hi, I am using Modelsim 6.2e with the Xilinx webpack 8.2. When I print the vhdl text from the text editor of Modelsim, the font size is very...

Hi, I am using Modelsim 6.2e with the Xilinx webpack 8.2. When I print the vhdl text from the text editor of Modelsim, the font size is very big. How to modify the font size in the printed paper? I do not find such dialogue box. Thank you very much.


Xilinx no longer ships with Modelsim MXE?

Started by HT-Lab in comp.arch.fpga11 years ago 4 replies

I received a Sigasi Editor update email which had the following statement: "Xilinx no longer ships ModelSim with ISE but now ships its own HDL...

I received a Sigasi Editor update email which had the following statement: "Xilinx no longer ships ModelSim with ISE but now ships its own HDL simulator that enables functional and timing simulations for VHDL, Verilog and mixed VHDL/Verilog designs: ISim." Is this correct? Although ISIM is not bad it is still a long way from being Modelsim (even though the MXE(starter) edition is fa...


Init BlockRAM for Modelsim

Started by David in comp.arch.fpga16 years ago

Hi, How can I initialize the Xilinx BlockRAMs without changing the Cores in the CoreGenerator? The solution suggested by ModelSim does not...

Hi, How can I initialize the Xilinx BlockRAMs without changing the Cores in the CoreGenerator? The solution suggested by ModelSim does not work because the Memory array is not visible in the Workspace. Does anyone have solved the same problem before? Thanks for your suggestions. Regards, David


Hi

Started by ram in comp.arch.fpga14 years ago 2 replies

Hi I am using modelsim for simulation and quartus 6.0 for remaining.I have generated custom netlist ffrom quartus.I want to simulate in...

Hi I am using modelsim for simulation and quartus 6.0 for remaining.I have generated custom netlist ffrom quartus.I want to simulate in modelsim .How to link library of cyclone device.How to do that.Can anybody help me.Thanking you


Viewing internal signals with ModelSim

Started by Joseph in comp.arch.fpga13 years ago 3 replies

Hi all, I am simulating a entity with Modelsim via Xilinx Webpack. Modelsim only displays the input/output signals of the simulated top...

Hi all, I am simulating a entity with Modelsim via Xilinx Webpack. Modelsim only displays the input/output signals of the simulated top entity. Is there a way of viewing the internal signals declared in the architecture of the entity without adding them to the port outputs of the simulated top entity? Thanks very much Regards Joseph