ModelSim version upgrade problem from 6.1c to 6.2c

Started by Weng Tianxiang in comp.arch.fpga14 years ago 1 reply

Hi, When my ModelSim version is upgraded from 6.1c to 6.2c, a new problem happens: When opening wave.do file, either created by 6.1c version...

Hi, When my ModelSim version is upgraded from 6.1c to 6.2c, a new problem happens: When opening wave.do file, either created by 6.1c version or 6.2c version, the following error information would appear: # WLF Error: Bad initial WLF parcel. WLF file is corrupt. # Cannot open file: C:/Weng/Simulation/CITO2/wave.do It means I cannot normally use 6.2c version of ModelSim, because comple...


Xilinx + Modelsim *Please Help Tonight*

Started by Ricky Stern in comp.arch.fpga16 years ago 2 replies

I am trying to use modelsim to do a timing simulation on a VHDL file I generated using xilinx. I generated the: ecc.sim.sdf and the...

I am trying to use modelsim to do a timing simulation on a VHDL file I generated using xilinx. I generated the: ecc.sim.sdf and the ecc_sim.vhdl. However in modelsim with I use these commands it give me an error at the 5th command. It will not vsim. cd {c:/ecc/lab1test/ecc_multiply} vlib work vmap simprim c:/modeltech_6.0b/examples/Modeltech_6.0bxilinx/simprim vcom ecc_sim.vhd vsim -...


Modelsim XE problem with Xilinx ISE 8.1i and 8.2i

Started by Dan K in comp.arch.fpga15 years ago

This is an all VHDL design. Modelsim XE is installed as full VHDL. Design uses a number of block rams built with Xilinx coregen, which produces...

This is an all VHDL design. Modelsim XE is installed as full VHDL. Design uses a number of block rams built with Xilinx coregen, which produces the VDHL and Verilog files along with a bunch of other files. Here's the problem that started showing up with ISE 8.1i webpack and is still there with ISE 8.2 full (not the webpack): When I first fire up the simulation, Modelsim sees the verilo...


How to oerform a functional simulation of a QuartusII design with Modelsim?

Started by Claudio in comp.arch.fpga15 years ago

Hi All, we are having troubles in simulating our design with QuartusII. We found that the QuartusII simulator is dramatically slow since...

Hi All, we are having troubles in simulating our design with QuartusII. We found that the QuartusII simulator is dramatically slow since every time we must perform the whole compilation procedure before simulating, even if we'd like to perform a functional (not timing) simulation; so we are now trying to use Modelsim. We set the QuartusII to launch Modelsim (through the NativeLink feature);...


co-sim for handel C with modelsim vs pure modelsim VHDL simulation

Started by Anonymous in comp.arch.fpga13 years ago 1 reply

Hi, has anybody tried using co-sim for Handel C with modelsim? I managed to set up the co-sim environment, and got the handel C code to...

Hi, has anybody tried using co-sim for Handel C with modelsim? I managed to set up the co-sim environment, and got the handel C code to work with my EDK generated microblaze environment (in VHDL). In short, I am using handel C to build a peripheral which i attached to microblaze via the FSL bus. The simulation works ok when I used Handel-C + VHDL using the cosim manager provided by PDK...


ModelSim path problem as fed by Xilinx ISE ver 8.2.03i

Started by Anonymous in comp.arch.fpga15 years ago 5 replies

Hi all, I am using ModelSim III XE 6.1e starter edition with ISE 8.2.03i and I am trying to do post-par simulation having built...

Hi all, I am using ModelSim III XE 6.1e starter edition with ISE 8.2.03i and I am trying to do post-par simulation having built everything successfully. I have the checkmark in the green circle for "Generate Post-Place & Route Simulation Model". In the Sources Window I select "Post-Route Simulation" and get the ModelSim Simulator in the Processes Window, with "Simulate Post-Place & Route M...


Testbench using Modelsim/VHDL - simple signal generation problem

Started by Anonymous in comp.arch.fpga16 years ago 11 replies

I'm not sure if this is VHDL or Modelsim issue (other than operator issue), so I'm posting in both groups. It looks like too simple a case to...

I'm not sure if this is VHDL or Modelsim issue (other than operator issue), so I'm posting in both groups. It looks like too simple a case to ask someone online, but I've been scratching my head too long on this. I'm relatively new to VHDL (and Modelsim as well). In a testbench, I'm doing a simple signal generation : - assert 'sig1' at a rising edge of a free running clock at some point ...


About ModelSim

Started by ZHI in comp.arch.fpga14 years ago 7 replies

Hi, I want to learn using textio. Here I use Read data from scr.txt to IP core RAM and Write them to the text1.txt. I wrote the codes here...

Hi, I want to learn using textio. Here I use Read data from scr.txt to IP core RAM and Write them to the text1.txt. I wrote the codes here but it doesn't work. Any suggestions about this is very appreciated. One more thing, when i use Modelsim to Run by step. It alway gives the error information and cannot finish the simulation. I don't what it means. ***************************************...


ModelSim, Virtex DCM, and clk0 phase problem

Started by Dan Braunstein in comp.arch.fpga17 years ago 1 reply

Has anyone experienced the clk0 being 180 deg out of phase with the DCM input clock during simulation (wave view) in ModelSim? I have clk0 going...

Has anyone experienced the clk0 being 180 deg out of phase with the DCM input clock during simulation (wave view) in ModelSim? I have clk0 going to clkfb through a bufg, just like what is described in the V-II Platform Handbook (jellybean simple implementation), but after lock, clk0 is 180 out of phase, so I do not get the wave that is shown in the modelsim wave view in the Handbook. My fi...


Accessing ModelSim Environment variables in Verilog code

Started by Nju Njoroge in comp.arch.fpga15 years ago 3 replies

Hello, I would like to access environment variables defined in ModelSim (6.0d) in my Verilog code so that I can use them with the `ifdef...

Hello, I would like to access environment variables defined in ModelSim (6.0d) in my Verilog code so that I can use them with the `ifdef construct. For instance, ModelSim allows you to access the "MODEL_TECH" environment variable, which is useful for employing `ifdef's on code you want that you want to be compiled for simulation, but ignored for hardware synthesis. In a similar vein, I ...


TCL testcase in Modelsim.

Started by bigyellow in comp.arch.fpga13 years ago 6 replies

Hello, Does anybody have experience on writing TCL testcase in Modelsim? I only have VHDL simulation license of Modelsim, I used to write...

Hello, Does anybody have experience on writing TCL testcase in Modelsim? I only have VHDL simulation license of Modelsim, I used to write both testbench and testcase in VHDL. But I feel VHDL is not that nice to implement testcase. So I am thinking to implement my testbench in VHDL, and write the testcases in TCL for my next project. Of course the verification should be self-checking. ...


Transport Delays in Modelsim

Started by Kevin Neilson in comp.arch.fpga14 years ago 6 replies

Has anyone ever been able to get Modelsim to model transport delays in Verilog? Verilog simulators, by default, use inertial delays, so if you...

Has anyone ever been able to get Modelsim to model transport delays in Verilog? Verilog simulators, by default, use inertial delays, so if you have an assignment such as this: assign #4 sig_out = sig_in; then any pulse on sig_in that is less than 4ns will get swallowed. Modeling transport delays prevents this from happening. Modelsim claims to model transport delays using the +tran...


peculiar process behavioral when using modelsim se 5.8d

Started by Hezi Hershkovitz in comp.arch.fpga16 years ago

when simulating the code below with modelsim SE 5.8d (and above), the CD, Sync, and WaitCnt don't get the correct values under reset ('1', '0',...

when simulating the code below with modelsim SE 5.8d (and above), the CD, Sync, and WaitCnt don't get the correct values under reset ('1', '0', and 1 respectively). instead, they get 'U','U', and 0. when running the simulation with Modelsim SE 5.8 they do get the correct values. ------------------------------------------------- signal CD :std_logic; signal Sync :std_logic; signal WaitCnt...


Usage of Xilinx Library elements in ModelSim simulation

Started by J?rgen in comp.arch.fpga17 years ago 2 replies

I like to simulate our design by using Xilinx library elements (RAMB16_s4_s4) with ModelSim SE plus 5.7d (on PC). While using the downloaded...

I like to simulate our design by using Xilinx library elements (RAMB16_s4_s4) with ModelSim SE plus 5.7d (on PC). While using the downloaded xilinx_lib_4.tcl file I obtain the following error messages: # Model Technology ModelSim SE vcom 5.7d Compiler 2003.05 May 10 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package vital_timing # -- Loading packa...


Conflict found between ActiveHDL6.1 and ModelSim SE

Started by Jay in comp.arch.fpga18 years ago 2 replies

When both of them were installed on my pc, I found: 1.ModelSim can't compile Xilinx library 2.ISE will give a fatal error when ActiveHDL try...

When both of them were installed on my pc, I found: 1.ModelSim can't compile Xilinx library 2.ISE will give a fatal error when ActiveHDL try generate post-PAR timing simulation model and they both can work well separately.


EDK + Modelsim simulation : Memory allocation failure

Started by Pasacco in comp.arch.fpga13 years ago 4 replies

Dear When I simulate one EDK project (with multi-processors), Modelsim reports an error "Memory allocation failure". I tested the EDK...

Dear When I simulate one EDK project (with multi-processors), Modelsim reports an error "Memory allocation failure". I tested the EDK project with 6 microblazes and it was okay. Now I am trying to simulate the EDK project with 12 Microblaze. What I did was 1. Implement the system using EDK. In Modelsim, 2. compile "system.vhd" and "system_init.vhd" 3. compile "testbench" 4. Loa...


exe file in modelsim

Started by fazulu deen in comp.arch.fpga14 years ago 1 reply

Hi all, Can anyone suggest me how to run an exe file in modelsim...I have tried using sccom -g basedes.cpp baseDesc.cpp...

Hi all, Can anyone suggest me how to run an exe file in modelsim...I have tried using sccom -g basedes.cpp baseDesc.cpp -Wno-deprecated.Compilation and linking was successful but i dont know the command to run an exe file Thanks in advance, fazal


Modelsim SE Simulation

Started by kris...@gmail.com in comp.arch.fpga15 years ago 7 replies

Hi, I use Modelsim SE 6.0 simulator for my projects. My Project is very big and it takes nearly 15 min for compilation. As the license is...

Hi, I use Modelsim SE 6.0 simulator for my projects. My Project is very big and it takes nearly 15 min for compilation. As the license is network one, after compilation, it says simulation license error - if license is not available. Is there a command available in modelsim to check license on network? Next, In my project only 3 to 4 files are changed frequently. Rest other files are not ...


Modelsim - SDF incompatibility

Started by Ruzica in comp.arch.fpga14 years ago

Hi, I am using Modelsim to simulate placed-and-routed Xilinx design. I have noticed that in some cases iopath from sdf is being treated as...

Hi, I am using Modelsim to simulate placed-and-routed Xilinx design. I have noticed that in some cases iopath from sdf is being treated as a transport delay and in some other as inertial delay, although the type of the cell is the same (for example, x_buf_pp). Could someone tell me why is this happening and is there a way to change it? Thanks in advance! Ruzica


Modelsim-SDF-Vital

Started by Ruzica in comp.arch.fpga14 years ago

Hi, I am using Modelsim to simulate placed-and-routed Xilinx design described in VHDL. I have noticed that in some cases iopath from sdf is...

Hi, I am using Modelsim to simulate placed-and-routed Xilinx design described in VHDL. I have noticed that in some cases iopath from sdf is being treated as a transport delay and in some other as inertial delay, although the type of the cell is the same (for example, x_buf_pp). Could someone tell me why is this happening and is there a way to change it? Thanks in advance!