Altera NIOS cyclone edition development board problem

Started by Jack in comp.arch.fpga16 years ago 5 replies

hi. i am going through software dev. tutorial that came with nios dev. kt for cyclone and whenever i tried to run insight debugger...

hi. i am going through software dev. tutorial that came with nios dev. kt for cyclone and whenever i tried to run insight debugger with byteblaster II, it always said "failed to connect. here is the command line: nios-debug lcd_demo1.srec # [nios-gdb-server] accepting gdb connection # [nios-gdb-server] connecting to OCI, ocibase 0x00920800 # [nios-gdb-server] ...using byteblaster (altLP...


NIOS II Sim

Started by Jerry in comp.arch.fpga16 years ago 3 replies

I replaced my NIOS I with a NIOS II and did a simulation. Hummm it seems to take a lot more CPU time with a NIOS II. Has anyone else...

I replaced my NIOS I with a NIOS II and did a simulation. Hummm it seems to take a lot more CPU time with a NIOS II. Has anyone else experienced this? ARRRRRGGGGGHHHHH Jer


NIOS simulation with modelsim -> strange behaviour

Started by Mancini Stephane in comp.arch.fpga17 years ago

Hi, I would like to simulate a NIOS system with modelsim but I have very strange results : it seems that the external SRAM (for the Nios Apex...

Hi, I would like to simulate a NIOS system with modelsim but I have very strange results : it seems that the external SRAM (for the Nios Apex dev board) is incorectly adressed by the NIOS processor. I'm using quartus 2.2 and sopc builder 2.8 (NIOS 3.0) Here is what I'm doing : - the system is minimal (a 32 bit nios, an UART, an on chip memory, the external SRAM and two user interfaces). ...


nios-run ignores kbd.

Started by Nigel Gunton CEMS STAFF in comp.arch.fpga16 years ago 3 replies

Hi, I'm having problems getting nios-run -t to function correctly. The development platform is Quartus 3 sp2, SOPC 3.02 on Linux, Apex...

Hi, I'm having problems getting nios-run -t to function correctly. The development platform is Quartus 3 sp2, SOPC 3.02 on Linux, Apex board. I'm using the standard_32 example provided with the Nios kit 3.2. This builds (SDK and the hardware) without apparent problem, synthesises and can be downloaded via the jtag interface. executing nios-run -t results in the peripherals test menu bei...


Why memory for this Nios II is still not enough

Started by fl in comp.arch.fpga12 years ago 6 replies

Hi, I am trying to use Nios II with one Stratix II (2S60) DSP board, not the Nios board. Even to use Nios /f in the simplest hello example,...

Hi, I am trying to use Nios II with one Stratix II (2S60) DSP board, not the Nios board. Even to use Nios /f in the simplest hello example, the following error message is still there. What is the problem? Thanks all. BTW, Using Quartus 7.2 subscription. **** Build of configuration Debug for project hello_world_1 **** make -s all includes Linking hello_world_1.elf... /cygdrive...


Nios II really available ?

Started by geoffrey brown in comp.arch.fpga16 years ago 5 replies

Has anybody actually received updates to their Quartus and Nios toolkits to support Nios II ? Geoffrey

Has anybody actually received updates to their Quartus and Nios toolkits to support Nios II ? Geoffrey


Nios - cyclone toolchain questions

Started by tns1 in comp.arch.fpga16 years ago 2 replies

I have downloaded the quartusIIwe, and used it to synthesize some modules for cyclone parts - works great. Now I would like to try SOPC...

I have downloaded the quartusIIwe, and used it to synthesize some modules for cyclone parts - works great. Now I would like to try SOPC builder and compile some C for an existing nios board, but am a little confused about the toolchain. QuartusII comes with cygwin, but it looks like there is no gcc, etc. for nios. Altera's site says the Gnupro tools for nios do not require a license, ...


Cygwin & Nios II

Started by Peter Sommerfeld in comp.arch.fpga15 years ago 4 replies

Hi, Awhile back I tried having Nios II and a separate cygwin (from cygwin.com) on the same machine, but ran into big problems. I now want to...

Hi, Awhile back I tried having Nios II and a separate cygwin (from cygwin.com) on the same machine, but ran into big problems. I now want to install the latest Nios II eval kit but I'm not sure if Altera has fixed things so they can co-exist. Does anyone have a stand-alone Cygwin and Nios II tools running fine on the same machine? I thought I'd ask beforehand because I sure don't want t...


Using gprof with Nios II

Started by steven derrien in comp.arch.fpga16 years ago 3 replies

Hi, Has anybody been trying to use gprof within the NIOS II IDE ? We have some problems regarding the profiling data that is send through the...

Hi, Has anybody been trying to use gprof within the NIOS II IDE ? We have some problems regarding the profiling data that is send through the jtag interface directly to the IDE console window. We had a look to the documentation but there is little information regarding the use of the profiler with the NIOS II. It seems that, to the difference of NIOS I, the profiling data is sent as ...


Nios II Going Live...

Started by Kenneth Land in comp.arch.fpga16 years ago 58 replies

Tomorrow is the big Nios II launch date, but info is already going...

Tomorrow is the big Nios II launch date, but info is already going up.... www.altera.com http://www.fpgajournal.com/articles/20040518_nios2.htm Full 32bit. 2X-4X faster than Nios I and starts at only 500 LE's. New IDE. New Compact Flash and other periferals.... Can't wait to get a hold of it. Ken


Nios II timing question

Started by essay in comp.arch.fpga15 years ago 4 replies

Hello, I have also posted this message on the niosforums site. Hopefully someone here will have an insight to my problem. I am developing...

Hello, I have also posted this message on the niosforums site. Hopefully someone here will have an insight to my problem. I am developing on a system that is very similar to the Nios II evaluation kit. I am trying to transfer data to and from the LAN91C111 Ethernet MAC but have noticed some problems. The MAC is connected to the Nios II in exactly the same way as on the demo board. It ...


Min. Reqmts For Altera Nios -- i.e Will it work on Parallax Cyclone FastPack?

Started by Ben Nguyen in comp.arch.fpga16 years ago 1 reply

Is the 50 mhz EP1C3T100C7 Cyclone have enough resources (LE) to synthesize the nios? For example, this board doesnt have any memory, what kind...

Is the 50 mhz EP1C3T100C7 Cyclone have enough resources (LE) to synthesize the nios? For example, this board doesnt have any memory, what kind of limits will that put on the nios processor?


Altera Nios II & PCI Compiler 4.1.0 Question

Started by Sander & Stieneke Odekerken in comp.arch.fpga14 years ago 2 replies

Hi, I'm using SOPC Builder and added some components, including NIOS II, external RAM and a PCI Host-Bridge (PCI Compiler 4.1.0). Is there,...

Hi, I'm using SOPC Builder and added some components, including NIOS II, external RAM and a PCI Host-Bridge (PCI Compiler 4.1.0). Is there, by coincidence, a reference design available of a system using Nios II and the PCI Compiler together? I know there is a reference design in the PCI Compiler User Guide, but it doesn't use the Nios II processor, which I really need in my design. Anot...


Nios II - Booting software from Flash

Started by Joseph Tan in comp.arch.fpga15 years ago 3 replies

Hi, Has anyone got NIOS software to boot from Flash? I'm working on a Stratix II-based design with onboard NIOS and peripherals (16MB...

Hi, Has anyone got NIOS software to boot from Flash? I'm working on a Stratix II-based design with onboard NIOS and peripherals (16MB flash, Ethernet, SDRAM etc). The Flash, Ethernet, and SDRAM components are wired to the Stratix-II via an Avalon tri-state bus, similar to the design on the Stratix Edition Nios development kit. A single Nios CPU core is running at 50MHz.on the Stratix II....


nios II stratix II handling interrrupts from uController

Started by badari in comp.arch.fpga14 years ago 2 replies

hi all! I'm using NiosII with StratixII. i wanted to get interrupts from a micro controller of 7.393MHz Oscillator which generates half...

hi all! I'm using NiosII with StratixII. i wanted to get interrupts from a micro controller of 7.393MHz Oscillator which generates half the oscillator clock. Nios works at 50Mhz. so what modification i need to do on nios


Basic questions about the Nios II.

Started by NickNitro in comp.arch.fpga13 years ago 9 replies

Hello. I'm getting a better outline of what's available and the differences between the different options, such as FPGAs and CPLDs. Although,...

Hello. I'm getting a better outline of what's available and the differences between the different options, such as FPGAs and CPLDs. Although, I've just come across Alteras "Nios II Embedded Processor" and to be honest it's thrown me off completely. - What is a soft-core processor? - It seems that Nios II isn't a physical product I buy, it appears to be an emulator running on top of any ...


Question about Altera NIOS II, Eclipse, Quartus subscription try version 9.1

Started by fl in comp.arch.fpga10 years ago

Hi, I am new to Altera Eclipse for quartus subscription 9.1 version. I want to learn NIOS programming. I go through the simpliest version...

Hi, I am new to Altera Eclipse for quartus subscription 9.1 version. I want to learn NIOS programming. I go through the simpliest version on 'Getting Started' part in "Nios II Software Developer's Handbook". I create a project step by step according to the handbook (I have no NIOS II evaluation board at home). The project is created with 'Nios II Application and BSP from Template' option. ...


Nios II Multiprocessor Collection run in command line

Started by Ewa in comp.arch.fpga13 years ago

Hi All, is there any chance to run Nios II Multiprocessor Collection in command line? I have the system with 2 cpus. I've tried to run...

Hi All, is there any chance to run Nios II Multiprocessor Collection in command line? I have the system with 2 cpus. I've tried to run the programs separately, but in that case mutex doesn't work properly. Perhaps smth wrong with cpu's ID value. Note: from Nios II IDE it works fine, when I use Nios II Multiprocessor Collection. Best regards, Ewa.


NIOS SDRAM controller simulation

Started by Anonymous in comp.arch.fpga16 years ago

I'm trying to simulate a NIOS based system with a altera_avalon_new_sdram_controller which is shared with the systembus. When I try to do a...

I'm trying to simulate a NIOS based system with a altera_avalon_new_sdram_controller which is shared with the systembus. When I try to do a write (ST) to the SDRAM I see that the cpu.the_sdram_s1.sdram_s1_chipselect is asserted. However the NIOS top level cpu.zs_cs_n_to_the_sdram_sdram_chip is not. If I replace the SDRAM target address of the ST instruction with a different different t...


Nios & off-chip memory

Started by amyler in comp.arch.fpga16 years ago 1 reply

Hi, I'm using a Nios to access off-chip memories via the SoPC-builer's external memory bridge. The Nios is 32-bit data, the memories are...

Hi, I'm using a Nios to access off-chip memories via the SoPC-builer's external memory bridge. The Nios is 32-bit data, the memories are 16-bit data. Using SignalTap I can see that Nios is only accessing even addresses in the external memory (using germs monitor commands and/or my own c-code). Has anyone there come across something like this before? Thanks in advance, Alan Myler