nios-convert

Started by evan in comp.arch.fpga16 years ago

Nios-convert is causing me grief. I am converting a 2249kB srec to a .mif but getting the following error message: ...

Nios-convert is causing me grief. I am converting a 2249kB srec to a .mif but getting the following error message: nios-convert A.srec c:\B.mif Out of memory! Does anyone know why this is occuring? I am working on a fairly decent machine. The .mif turns out (when it was working) to be around 7500kB. Evan


Problem with user defined logicinterface in Nios

Started by Thorsten Klatt in comp.arch.fpga18 years ago

Hi, I am using Quartus 2.2 SP2 with Nios 3.0 I have fit my logic with the SOPC into the Niosstructure and generating and compiling of this...

Hi, I am using Quartus 2.2 SP2 with Nios 3.0 I have fit my logic with the SOPC into the Niosstructure and generating and compiling of this is fine. I am testing on a stratix devel. board. Programming of the fpga works out fine too. The problem is, that no programm runs on the nios. (i.e. hello_world) The srec file is downloaded to the chip and then just the terminal appears. (nr -r hell...


Unable to Download on STRATIX (EP1S25F1020C5) Development Board using NIOS IDE

Started by sankalp.singhal in comp.arch.fpga16 years ago 8 replies

hi group, I have just started using NIOS II with Quartus II ver 4.2 ..I tried a simple project having a NIOS CPU, an...

hi group, I have just started using NIOS II with Quartus II ver 4.2 ..I tried a simple project having a NIOS CPU, an onchip-memory(16Kbytes)and an led PIO. Using IDE i made a C application program and included the respective .ptf file..after succesfully building the the project , when i am RUNning the application it is giving a warning in the console-- "Using cable "ByteBlasterII [LPT...


Nios II = Microblaze

Started by Stifler in comp.arch.fpga17 years ago 26 replies

Altera finally wakes up. They realize that the window register type architecture is not good for FPGAs and probably in general. They can no...

Altera finally wakes up. They realize that the window register type architecture is not good for FPGAs and probably in general. They can no longer support their own marketing hype about how great Nios I is. If Nios 1 was so great, why did it need a complete redesign and rearchitecture? It means it was poor. That's the only reason you do a complete redesign. I believe they have switched to 32 ...


Nios - Ethernet Frame Format

Started by Colin in comp.arch.fpga17 years ago 3 replies

Hi, I would like to know if the Ethernet packets sent through the Nios Ethernet Kit, do they have a 32-bit CRC as the trailer. If there is...

Hi, I would like to know if the Ethernet packets sent through the Nios Ethernet Kit, do they have a 32-bit CRC as the trailer. If there is a CRC trailer does the Nios software and hardware check this automatically? And if there isn't a 32-bit CRC trailer, how can we calculate and add this? Thanx


Nios - Ethernet Frame Format

Started by Colin in comp.arch.fpga17 years ago

Hi, I would like to know if the Ethernet packets sent through the Nios Ethernet Kit, do they have a 32-bit CRC as the trailer. If there is...

Hi, I would like to know if the Ethernet packets sent through the Nios Ethernet Kit, do they have a 32-bit CRC as the trailer. If there is a CRC trailer does the Nios software and hardware check this automatically? And if there isn't a 32-bit CRC trailer, how can we calculate and add this? Thanx


Nios II & obj copy this Unknown!!!!!

Started by Jjletodoc in comp.arch.fpga16 years ago

Hi There, I am an Nios developer , i build toons of project for this excellent soft-core, now i migrate to Nios II, nothing problem except...

Hi There, I am an Nios developer , i build toons of project for this excellent soft-core, now i migrate to Nios II, nothing problem except one! i need to convert an .out file to binary using nios2-elf-objcopy ... the line is : nios2-elf-objcopy -O binary xxxx.out xxxxx.bin well the binary come is bigger than the .out ,, normally is the contrary!!!!! i've used every parameter to resi...


WTB NIOS-II kit

Started by Neo in comp.arch.fpga16 years ago 7 replies

Hi, I wanted to buy a NIOS-2 eval kit, used or new. can anyone point me to appropriate sellers who, if selling new, are offering...

Hi, I wanted to buy a NIOS-2 eval kit, used or new. can anyone point me to appropriate sellers who, if selling new, are offering discounts. thanks.


Nios reset behavior

Started by tns1 in comp.arch.fpga17 years ago 4 replies

I am trying to understand the low level startup sequence on a custom Nios board. When the Nios (3.2) resets, what determines where it fetches...

I am trying to understand the low level startup sequence on a custom Nios board. When the Nios (3.2) resets, what determines where it fetches its very first instruction? Is it always from the onchip bootstrap area or is this configurable? I don't have the OCI so I assume I can't just step thru from reset on my target (with gdb). As I understand it, SOPC(4.0) compiles my custom bootstrap...


new to NIOS II

Started by Amit in comp.arch.fpga13 years ago 2 replies

Hello group, Recently I have started to learn NIOS. I will appreciate it if somebody knows any good online resource or book that I can...

Hello group, Recently I have started to learn NIOS. I will appreciate it if somebody knows any good online resource or book that I can use. Thanks, Amit


Altera Nios Ethernet Development Kit: "spurious interrupt number: 0000 001C"

Started by Colin in comp.arch.fpga17 years ago 2 replies

Hi, I'm trying to use the Nios Ethernet Development Kit to run a simple example program, it build fine, but when I run it it comes up with...

Hi, I'm trying to use the Nios Ethernet Development Kit to run a simple example program, it build fine, but when I run it it comes up with a "spurious interrupt number: 0000 001C" error. Does anyone know how to solve this problem. I'm using the Excalibur Apex development board, Nios 3.0, and the Nios Ethernet Development Kit 2.0. Thanx.


NIOS - newbie

Started by Nahid in comp.arch.fpga16 years ago 1 reply

I'm trying to implement the following C++ code using NIOS processor's native instruction set. int A; int B; for (int i = 0; i < B; i++) ...

I'm trying to implement the following C++ code using NIOS processor's native instruction set. int A; int B; for (int i = 0; i < B; i++) A = (A <


User peripherals within a Nios system

Started by Frank van Eijkelenburg in comp.arch.fpga15 years ago 2 replies

Is it possible to have a connection between two seperate user peripherals inside a Nios 2 system? Or do I have to route the signals outside the...

Is it possible to have a connection between two seperate user peripherals inside a Nios 2 system? Or do I have to route the signals outside the Nios 2 system and connect them at toplevel (like below)? nios_system : entity work.nios_system port map ( clk => sys_clk, reset_n => locked, out_port_from_the_usr_periphera


How to generate downloadable Nios II cpu ?

Started by fl in comp.arch.fpga13 years ago 2 replies

Hi, We have Quartus II 7.2 subscription edition software. Although it is claimed that it supports Nios II cpu, I cannot generate downloadable...

Hi, We have Quartus II 7.2 subscription edition software. Although it is claimed that it supports Nios II cpu, I cannot generate downloadable .sof file for my first Nios project.The following message pop up at the last compiler process(EDA netlist generation). Could you tell me what is wrong here? Thanks. Error: Can't generate netlist output files because the file "C:/altera/...


Q: Demo Altera NIOS II SOPC limitations

Started by MarkAren in comp.arch.fpga13 years ago 3 replies

Hi All, I have just compiled a NIOS II core into Cyclone I part (I was given an old MJL demo board) and compiled some trivial C. Everything...

Hi All, I have just compiled a NIOS II core into Cyclone I part (I was given an old MJL demo board) and compiled some trivial C. Everything seems to work as advertised. I still haven't figured out the time limited nature of the NIOS II SOPC builder, could someone enlighten me please. There seems to be a 60 minute limit between creating the FPGA code (Verilog) and compiling a new FPGA im...


Altera nios-debug via JTAG

Started by evan in comp.arch.fpga16 years ago

Hi, I have been trying to debugg a simple "hello world" program running in an Altera Cyclone device with Nios 32 (including OCI-Core) via...

Hi, I have been trying to debugg a simple "hello world" program running in an Altera Cyclone device with Nios 32 (including OCI-Core) via JTAG. I can use serial comms for the upload but I need the serial communications available during execution. The problem is that the JTAG upload gives me the following error: # 2005.08.29 13:34:24 (*) nios-init-mdi -i WARNING: Do not attempt to ...


anybody ported Jrunner to NIOS I/II??

Started by ron proveniers in comp.arch.fpga17 years ago

On an embedded test-platform we have to configure a remote Altera Cyclone device via its JTAG chain. Our test-platform also has an Altera...

On an embedded test-platform we have to configure a remote Altera Cyclone device via its JTAG chain. Our test-platform also has an Altera Cyclone fpga with a NIOS I SOC. We like to program the remote Cyclone via its JTAG. Right now we think the best method is to port the Altera Jrunner software to the NIOS I. Questions: 1- has anybody done this before (the NIOS port)? 2-what is the max.c...


NIOS II fmax on a Cyclone

Started by Anonymous in comp.arch.fpga15 years ago 1 reply

Dear everybody, I have developed a NIOS II based project which must run on a Cyclone with speed grade 7. The project contains only a NIOS...

Dear everybody, I have developed a NIOS II based project which must run on a Cyclone with speed grade 7. The project contains only a NIOS II/f configuration which includes the following pheriperals: - SRAM interface designed with user custom logic - common flash interface - one interval timer - three uarts - two tightly coupled on-chip memory blocks - one on-chip memo...


Nios performance

Started by Piotr Wyderski in comp.arch.fpga16 years ago 9 replies

Hello, how fast a Nios processor can be if embedded in a speed grade 6 Cyclone FPGA? What is the approximate maximum reachable clock...

Hello, how fast a Nios processor can be if embedded in a speed grade 6 Cyclone FPGA? What is the approximate maximum reachable clock frequency? Best regards Piotr Wyderski


Is it worth learning SOPC Builder, DSP Builder & Nios Processor?

Started by jjli...@hotmail.com in comp.arch.fpga15 years ago 6 replies

Hello, I've been seeing more training at Altera concerning their SOPC Builder, DSP Builder & the Nios Processor so I wanted to ask anyone...

Hello, I've been seeing more training at Altera concerning their SOPC Builder, DSP Builder & the Nios Processor so I wanted to ask anyone if these tools are gaining acceptance in the engineering world? A co-worker used the Nios processor a few years ago and said that it was slow so they didn't use it in their project. Are these tools useful for high-speed applications? If anyone can comment o...