nios2 flash programmer

Started by Jedi in comp.arch.fpga16 years ago 1 reply

According to the Altera NIOS docs there are premade .sof config files for flashing an own image onto a cyclone ep1c20 NIOS board. But none of...

According to the Altera NIOS docs there are premade .sof config files for flashing an own image onto a cyclone ep1c20 NIOS board. But none of the premade restore/flash design images work with the nios2 flash programmer...also not when make a new one from scratch with this mk_target_board script. Any hints or someone has a working .sof for ep1c20 NIOS kit? thanx in advance rick


NIOS II / Cyclone II - Multiply, Barrel Shift and Divide

Started by Jon Beniston in comp.arch.fpga17 years ago 1 reply

Hi, When targeting the Cyclone II, the NIOS II/f configuration in SOPC builder doesn't seem to list support for either...

Hi, When targeting the Cyclone II, the NIOS II/f configuration in SOPC builder doesn't seem to list support for either multipler, barrel-shifter or divide. Support for these only seems to be available when the target is a Stratix device. Is this correct? Is it not possible to get h/w multiply support on the Cyclone II? I'm using the eval version of NIOS II. Cheers, Jon


NIOS II power-on reset

Started by Alessandro Strazzero in comp.arch.fpga16 years ago 2 replies

Dear everybody, I have a problem on some production boards based on the Altera Cyclone FPGA. The boards have installed NIOS II CPU. The...

Dear everybody, I have a problem on some production boards based on the Altera Cyclone FPGA. The boards have installed NIOS II CPU. The problem regards the power-on sequence because some boards are not able to power-up correctly (seems NIOS II CPU doesn't execute first operative code). The development was made on a C7 speed grade FPGA and I didn't experience such problem. The boards wher...


Hardware in the loop simulation for Altera design

Started by jfh in comp.arch.fpga15 years ago 4 replies

Hi, I am presently involved in a project dealing with a pretty large design in a Stratix II GX chip with a Nios II processor. Is there anyway...

Hi, I am presently involved in a project dealing with a pretty large design in a Stratix II GX chip with a Nios II processor. Is there anyway to perform hardware in the loop simulation where the Nios II would be running on a board while modelsim is simulating the design ? Does anyone have an advice as to how simulation times could be improved when involving Nios II processor ? Best rega...


Nios Clock Frequency

Started by Maxlim in comp.arch.fpga18 years ago 6 replies

Hello, I'm trying to operate the nios processor with my crypto-processor . The default clock frequency (33.33 MHz) is too...

Hello, I'm trying to operate the nios processor with my crypto-processor . The default clock frequency (33.33 MHz) is too slow for fast cryptosystem performance. I'd tried to get another clock with 50 MHz frequency through PLL and generate the nios processor with 50 MHz in the clock setting. The system still can operate correctly with some simple application on it's own. B...


NIOS 2 memory limitations

Started by George in comp.arch.fpga17 years ago 5 replies

I'm converting a NIOS design to a NIOS 2 design. The end product has a large number of 256MBit FLASH devices (19). I've mapped all...

I'm converting a NIOS design to a NIOS 2 design. The end product has a large number of 256MBit FLASH devices (19). I've mapped all the periferrals to low mamory 0x000 to 0x2000 and then one 256 MBit SDRAM 0x0200 0000 (spaces added for clarity) I then start adding FLASH devices at 0x0400 0000. All goes well till I try to place FLASH at 0x1000 0000. I get a compiler error messages: "Addres...


Debugging software in an ACEX device with Nios 32 via JTAG

Started by Joe Sabater in comp.arch.fpga18 years ago 2 replies

Hi, I have been debugging a software application running in an Altera APEX device with Nios 32 (including OCI-Core) via JTAG with no problem...

Hi, I have been debugging a software application running in an Altera APEX device with Nios 32 (including OCI-Core) via JTAG with no problem at all. Now, I am trying to do the same with an ACEX (EP1K100FC256-2) with no success. The problem seems to be when the debugger tries to connect to the remote target via JTAG. After issuing a "nios-debug" command under SOPC Builder shell I get the fo...


Using C++ on NIOS

Started by Nigel in comp.arch.fpga17 years ago 1 reply

We have just started writing a small application on the NIOS IDE II (version 1.0.0, build 316). I want to develop it in C++, but it...

We have just started writing a small application on the NIOS IDE II (version 1.0.0, build 316). I want to develop it in C++, but it won't recognise C++ syntax, (class, new etc), so clearly I need to do something to enable C++, but I can't find anything. I have found similar problems on the forums/groups, but none with any answers. The closest one was to use "extern "C"{...} around the #inc...


[ALTERA] NIOS-II + MMU + FPU

Started by Markus Meng in comp.arch.fpga17 years ago 5 replies

Hi all, I just wonder if someone in the US could comit the following: ALTERA will bring out an update for its SOPC set featuring the MMU...

Hi all, I just wonder if someone in the US could comit the following: ALTERA will bring out an update for its SOPC set featuring the MMU and optional a FPU for the NIOS-II system. These enhancements shall be availabel this year? This would make it possible to run standard unix like Linux (MMU required) ... Best Regards Markus


Nios 2 Cyclone II board problem with simple logic

Started by magic in comp.arch.fpga11 years ago 7 replies

I have the Nios 2 board with cyclone II like this: http://www.altera.com/products/devkits/altera/kit-nios-2c35.html My problem is that I can't...

I have the Nios 2 board with cyclone II like this: http://www.altera.com/products/devkits/altera/kit-nios-2c35.html My problem is that I can't implement very simple program on the fpga. On the beginning I want use switches and leds to view that my program is running. When I plug in the power adapter to the board, the led factory is on( Is this mode I red in the documentation is running the ...


nios board, apex, tutorial doesn't work

Started by chi in comp.arch.fpga17 years ago 2 replies

Hi, friends, I'm following Altera Nios hardware tutorial for apex development board. I cannot run the hello_nios.srec SDK...

Hi, friends, I'm following Altera Nios hardware tutorial for apex development board. I cannot run the hello_nios.srec SDK display: nios-run: Ready to download hello_nios.srec over COM1: at 115200 bps : Press CPU Reset (or CLEAR) on target board to begin download : Type Control-C to exit the program : Waiting for target..... Did anybody meet this problem? Tha...


Can't do a single byte read in Nios?

Started by Kenneth Land in comp.arch.fpga17 years ago 5 replies

Hello, I'm having a problem reading a single one byte register on a Nios/Cyclone board. I've seen this on the devkit board as well. Every...

Hello, I'm having a problem reading a single one byte register on a Nios/Cyclone board. I've seen this on the devkit board as well. Every time I read a single memory location, the Nios is automatically generating reads for the next 3 locations as well. This causes bad things to happen when you are reading a location that is within 3 bytes of a location that does not want to be read. ...


Does SPI from NIOS II work?

Started by vladimir in comp.arch.fpga16 years ago 1 reply

Hello to anyone!!! I've made some NIOS design with SPI and wrote small source code .... while(1) { usleep(10); ...

Hello to anyone!!! I've made some NIOS design with SPI and wrote small source code .... while(1) { usleep(10); alt_avalon_spi_command(SD_BASE, 0, 6, write_data, 1, read_data, flags); } .... but when I saw SCLK on Proto2 by oscilloscope, the SCLK's pin was "0" always, SS_n was changing, MOSI was "0" an...


NIOS Board Stratix Edition - FPGA won't configure

Started by vadim in comp.arch.fpga17 years ago 6 replies

I am having problem with my NIOS Stratix Board. I am not able to download just my own, simple, compiled VHDL code onto the Stratix FPGA. The...

I am having problem with my NIOS Stratix Board. I am not able to download just my own, simple, compiled VHDL code onto the Stratix FPGA. The device is EP1S10F780C6ES. After JTAG (ByteBlaster) download finishes, the board resets and MAX configuration-device loads Stratix with the default configuration stored in the on-board FLASH memory (which is a NIOS based server thingy). I tried loading ...


NIOS II + USB 2.0 host

Started by Anonymous in comp.arch.fpga16 years ago 6 replies

Hi, We will soon be using the Nios II as embedded controller and we would like to add a High Speed (HS) USB 2.0 hosting feature that is...

Hi, We will soon be using the Nios II as embedded controller and we would like to add a High Speed (HS) USB 2.0 hosting feature that is capable or providing a sustained transfer rate of 20 MBytes/sec. to an external HS USB 2.0 device. I realize that there are a limited number of HS USB 2.0 hosts devices/IP cores currently available. The Phillips ISP1761 is the only HS USB 2.0 component...


Why does Nios cannot pass make?

Started by fl in comp.arch.fpga13 years ago 7 replies

Hi, I want to learn Nios with its examples: hello. Although the environment is correct, see...

Hi, I want to learn Nios with its examples: hello. Although the environment is correct, see below: SOPC_KIT_NIOS2=C:\altera\72\quartus\nios2eds I have check it both on control panel and cmd window. The following error message apperes. I can see both app_rules.mk and gnu_rules.mk exist at the build directory. What is wrong with that? Thanks in advance. --------------------------...


NIOS 2 HAL, libraries, ...

Started by Vanheesbeke Stefaan in comp.arch.fpga17 years ago 3 replies

Hello, I did a lot of work since the begining of NIOS(1) to put some libraries toghether with stuff that wasn't supported those days. Now with...

Hello, I did a lot of work since the begining of NIOS(1) to put some libraries toghether with stuff that wasn't supported those days. Now with Nios2 it seems to be impossible to make your own library? Or do I miss something. I can generate syslibs and other things I dont'really need, but not an ordenary archive (that is of course linked in before the standard C (or is it newlib now)). I...


Nios software IDE

Started by Frank van Eijkelenburg in comp.arch.fpga15 years ago 5 replies

Hi, I am trying to create a project within the nios software ide (which is based on eclipse). I want to have my project and source files on a...

Hi, I am trying to create a project within the nios software ide (which is based on eclipse). I want to have my project and source files on a different location as the .ptf file is. Is this possible? If I have my workspace at location A and create a new project I have to tell where the .ptf file is which describes my nios system. Let's say this file is at location B. The project wizard ...


nios c++ and ethernet [may by ot?]

Started by g.k. in comp.arch.fpga17 years ago 6 replies

Hi all! I just started to use an apex-board with nios-softcore and want to write some programs using the plugs-library in c++! I've already...

Hi all! I just started to use an apex-board with nios-softcore and want to write some programs using the plugs-library in c++! I've already done some experiments and have two questions: 1. I would like to know if using c++ is okay or if there are any backdrops (speed, size, ...)? 2. I was not able to put c++ together with the plugs library. The compiler has no problems but the linker ma...


Network Communication Using Nios Daughter Board

Started by Colin in comp.arch.fpga17 years ago

Hi, My partner and I are trying to implement a network bridge using the APEX20KE Nios Development board and Nios Ethernet Daughter Board. ...

Hi, My partner and I are trying to implement a network bridge using the APEX20KE Nios Development board and Nios Ethernet Daughter Board. As part of this network bridge we need to be able to recieve all Ethernet packets and be able to strip the headers (which we have been able to do). And then create new headers, create another Ethernet packet with the new header and send that (which we ...