Help required on Ethernet with FPGA

Started by renupriya in comp.arch.fpga12 years ago 1 reply

Hi .. I'm working on a project which involves a design that has NiOS II processor, DDRSDRAM, SSRAM, a custom Ethernet MAC and other...

Hi .. I'm working on a project which involves a design that has NiOS II processor, DDRSDRAM, SSRAM, a custom Ethernet MAC and other components and I've to run an application on it.. I use NiOS II embedded Evaluation board(Cyclone III), quartus 8.1 web edition. Since I'm new to Altera, I would like to start with a simple design with an ethernet MAC , then send and recieve packets through...


Many UARTs on Avalon bus with NIOS cpu

Started by Anonymous in comp.arch.fpga17 years ago

I am looking for a nice idea of hooking up many (12) simplified UART devices to NIOS II cpu using Avalon bus and fitting everything in Altera...

I am looking for a nice idea of hooking up many (12) simplified UART devices to NIOS II cpu using Avalon bus and fitting everything in Altera Cyclone FPGA. The problem I see is all UARTs are using one baudrate generator with 8 outputs for TX/RX clocks selectable for each UART. What would be the best way of incorporating such components into one SOPC? Or... maybe is there a way to make a mega-...


From whence the MAC on an Altera NIOS devel kit board?

Started by H. Peter Anvin in comp.arch.fpga17 years ago 4 replies

Hi all, I just noticed yesterday that according to the schematic there is no configuration EEPROM for the NIC on the Altera Nios development...

Hi all, I just noticed yesterday that according to the schematic there is no configuration EEPROM for the NIC on the Altera Nios development kit (Cyclone edition.) Yet my board has a MAC which looks relatively random (00:07:ed:0b:06:81). 00:07:ed is a prefix assigned to Altera. So... where is this number stored or derived from, if there is no EEPROM? I'd like my own design to be compa...


Cyclone and NIOS II

Started by GMM50 in comp.arch.fpga16 years ago

Is any using a Cyclone FPGA and NIOS II CPU? Specifically I'm having trouble booting from FLASH. THe boot sequence it to copy FLASH contents...

Is any using a Cyclone FPGA and NIOS II CPU? Specifically I'm having trouble booting from FLASH. THe boot sequence it to copy FLASH contents into DRAM then run out of DRAM. I can load directly into DRAM using the JTAG interface and all is OK. But running freestanding from a power up in NG. Is anyone able to accomplish this? George


Nios II interrupt

Started by Frank van Eijkelenburg in comp.arch.fpga15 years ago 1 reply

Hi, I am new to the Nios II core. I have built a simple system with a timer which is set as periodically timer. I have registered an...

Hi, I am new to the Nios II core. I have built a simple system with a timer which is set as periodically timer. I have registered an interrupt service routine: alt_irq_disable(TIMER_0_IRQ); res = alt_irq_register(TIMER_0_IRQ, NULL, timer_isr); With this code I still come in my installed ISR. So registering is also enable the interrupt. Is that correct, is there a way to reg...


Mailing list for NIOS kit/Lancelot hackers

Started by Anonymous in comp.arch.fpga17 years ago 1 reply

Hi all, I have no idea how big this community is, but I've been trying to set up a mailing list for people who hack the Altera NIOS...

Hi all, I have no idea how big this community is, but I've been trying to set up a mailing list for people who hack the Altera NIOS kits (APEX/Cyclone/Stratix) and especially using the Lancelot boards from www.fpga.nl. This may sound rather restrictive, but the hope is that there will be enough of a group that we can trade designs around. The subscription/archives page is at: h...


Nios II dev board

Started by Dario in comp.arch.fpga15 years ago

Hi everybody, I started to develop my fir filter with Quartus and Nios II dev board, with an Altera Stratix II EP2S60ES. The problems are...

Hi everybody, I started to develop my fir filter with Quartus and Nios II dev board, with an Altera Stratix II EP2S60ES. The problems are starting now, when I'm loading the .soc file on the FPGA. I put the "other pin's tree-state" option (so MAX processor doesn't reload factory config), but the project doesn't work. I think there are some problems on pin assignments, but I followed the pin...


Could someone tell me NIOS II/MB performance on this benchmark?

Started by Tommy Thorn in comp.arch.fpga13 years ago 5 replies

I trying to get a feel for how the performance of my (so far unoptimized) soft-core stacks up against the established competition, so it would...

I trying to get a feel for how the performance of my (so far unoptimized) soft-core stacks up against the established competition, so it would be a great help if people with convenient access to Nios II / MicroBlaze respectively would compile and time this little app: http://radagast.se/othello/endgame.c (It's an Othello endgame solver. I didn't write it) and tell me the configuration. In ...


Using Altera Nios II Stratix II dev kit just as FPGA.

Started by Anonymous in comp.arch.fpga15 years ago

Hello. Got this board without any intention to use Nios, but just to use EP2S60 chip. Drawed very simple schematics, loaded it via EPCS...

Hello. Got this board without any intention to use Nios, but just to use EP2S60 chip. Drawed very simple schematics, loaded it via EPCS config port (using Active Serial Programming method), powered it, and all LEDs are blinking, with about 2Hz frequency, except of those LEDs which was used in project. However, when one of LEDs must be turned on regarding my goal, it blinking modulated by ...


anyone using nios kit APEX?

Started by chi in comp.arch.fpga17 years ago

Hello, I'm using Nios Development Kit (general purpose, APEX). Is it outdated? It seems hard to find reference. All references are...

Hello, I'm using Nios Development Kit (general purpose, APEX). Is it outdated? It seems hard to find reference. All references are talking about Cyclone and Stratix. I even could not find the software development tutorial for APEX. I'm new to this tool suit. Does anyone have good suggestions to shorten time to hand on? Thanks! Chi


Help for Altera Nios II Cyclone EP1C12 evaluation kit!

Started by Jack Zkcmbcyk in comp.arch.fpga15 years ago 2 replies

Hello out there! I have purchased an Altera Nios II Cyclone based (EP1C12F324) evalution kit a while ago and didn't get to work with until...

Hello out there! I have purchased an Altera Nios II Cyclone based (EP1C12F324) evalution kit a while ago and didn't get to work with until recently. At first I was happy to see how quickly I got the board up and running and interacting with my PC through an Ethernet LAN and serving web pages using the uClinux on-board http server. Having had enough of the demo I started develo...


Problems with NIOS II PIO interrupt

Started by horst in comp.arch.fpga15 years ago 5 replies

Hi, I've some trouble with NIOS II PIO interrupts and need some help. The pio port is configured as follows: Width= 2 bits Both input and...

Hi, I've some trouble with NIOS II PIO interrupts and need some help. The pio port is configured as follows: Width= 2 bits Both input and output ports (not tri-state) Synchronously capture: Rising Edge IRQ= edge sensitiv I dont want to use HAL to keep the code size small, that's why I use alt_main. static void AudioCodecInISR(void* context, alt_u32 id) { volatile int inChL = 0; ...


Using Altera libraries for Nios Dev Board

Started by Justin in comp.arch.fpga17 years ago 2 replies

Hi, I'm currently working on a project at my university for testing and developing rate based protocols and I've been having some...

Hi, I'm currently working on a project at my university for testing and developing rate based protocols and I've been having some problems with my dev board. I've been using the Altera Nios proffesional dev board (with stratix FPGA). So far I've ran tests with UDP (over 2 dev boards) to test the utilization of my network, which is 100 Mbps and I keep getting numbers just under 10 Mbps. I'v...


Source code for NIOS GNU toolchain

Started by Jon Beniston in comp.arch.fpga17 years ago 5 replies

Does anyone know where I can download the source to the NIOS GNU toolchain? Altera's web site gives some...

Does anyone know where I can download the source to the NIOS GNU toolchain? Altera's web site gives some instructions: http://www.altera.com/support/kdb/rd11272000_7307.html But when logging in to the FTP site, I can only see empty directories. Any suggestions? Cheers, JonB


Download Nios II evaluation version today

Started by Alan Calac in comp.arch.fpga17 years ago

I know there has been some interst here, so I thought I'd mention that there's an evaluation version of the Nios II processor now available from...

I know there has been some interst here, so I thought I'd mention that there's an evaluation version of the Nios II processor now available from Altera's website. Check it out at: https://www.altera.com/support/software/download/sof-download_center.html --Alan


NIOS II & CS8900?

Started by vladimir in comp.arch.fpga17 years ago 2 replies

I've made a board with CS8900 for proto of NIOS Development kit board. It works very strange, I read internal registers and sometimes they was...

I've made a board with CS8900 for proto of NIOS Development kit board. It works very strange, I read internal registers and sometimes they was read correctly but in generaly incorrectly. Writing is correctly as seem to me. I'm using core of SOPC. Maybe someone gives me some advise. Thx.


Smart card ISO 7816 and NIOS Altera

Started by Giaccaglini Giorgio in comp.arch.fpga18 years ago

I want to implement a smart card reader on a FPGA Cyclone Altera with NIOS processor inside. Do you know any device driver (free or not) ISO...

I want to implement a smart card reader on a FPGA Cyclone Altera with NIOS processor inside. Do you know any device driver (free or not) ISO 7816 compatible? Thanks for your help Giaccaglini Giorgio Aethra Italy


regarding RTOS in NIOS II

Started by sriman in comp.arch.fpga14 years ago 1 reply

hi everyone i am trying to use RTOS in NIOS processor. After going through its documentation i found that UC/OS2 and UClinux are the two...

hi everyone i am trying to use RTOS in NIOS processor. After going through its documentation i found that UC/OS2 and UClinux are the two versions avaliable. I am interfacing my design to a Ethernet. i am using a DE2 board. i found that UClinux has got native TCP/IP protocols that wil help in easy interfacing of the WLAN module which i am using. But the problem what i am facing is i d...


Nios II problem

Started by Frank Buss in comp.arch.fpga14 years ago 5 replies

At work I'm using a Nios CPU with Quartus 7.1. I've configured it with 512 bytes data and instruction cache, and it uses internal RAM. I have a...

At work I'm using a Nios CPU with Quartus 7.1. I've configured it with 512 bytes data and instruction cache, and it uses internal RAM. I have a struct like this: struct Something { alt_u16 foo; alt_u16 bar; }; When modifying "foo" in a loop in main and "bar" of the same object in an interrupt, it looks like sometimes it behaves like the interrupt overides both variables, e.g. main...


Need a SPI 4?

Started by freechip in comp.arch.fpga15 years ago 1 reply

Hi I am working on 10 Gb Ethernet project. I am going to use a NIOS II in a Stratix II or a Stratix GX. I don't know yet. I have seen 2...

Hi I am working on 10 Gb Ethernet project. I am going to use a NIOS II in a Stratix II or a Stratix GX. I don't know yet. I have seen 2 development boards for this high bandwith. Normally, the interface SPI (System Packet Interface) is used between the fpga and a NPU. I don't use a NPU but a NIOS II in the fpga! So I think I can choose a development board whose within the SPI is not sup...