DCM driving multiple OBUF's ... skew in between ...

Started by Markus Meng in comp.arch.fpga14 years ago 3 replies

Hi all, a simple question: We intend to use a DCM in a Virtex-II Pro to drive multiple OBUF's but only ne feedback signal - of course. What...

Hi all, a simple question: We intend to use a DCM in a Virtex-II Pro to drive multiple OBUF's but only ne feedback signal - of course. What is the best way to minimize the delay difference between the OBUF's? Any help would be appreciated. Markus


using FPGA editor to set IOSTANDARD

Started by Steve Ravet in comp.arch.fpga7 years ago 4 replies

I need to add an output pin to my design (virtex6), driven constantly high. I've added a new OBUF, OLOGIC, and TIEOFF, and created the routes...

I need to add an output pin to my design (virtex6), driven constantly high. I've added a new OBUF, OLOGIC, and TIEOFF, and created the routes between them. I have one DRC warning, that the ISTANDARD of the OBUF isn't set. If I look at the properties of the OBUF I see that there is nothing in the OSTANDARD parameter. It should be LVCMOS25. How do I change it? It doesn't seem to be ed...


using FPGA editor to add a new output pin

Started by Steve Ravet in comp.arch.fpga7 years ago 5 replies

I thought this would be easy but I'm having a problem routing one of the wires. I need to create a new output from my fpga, tied high (LX760). ...

I thought this would be easy but I'm having a problem routing one of the wires. I need to create a new output from my fpga, tied high (LX760). What I've done so far: Added a new OBUF H36(and set the OSTANDARD, SLEW, and DRIVE, thanks Ed). Edited the OBUF OUTMUX and OINMUX to create a path from O to the pad. Added a new OLOGIC X0Y318 and created a path from D1 to OQ. Selected OBUF.O...


OBUF gate delay

Started by Anonymous in comp.arch.fpga9 years ago 3 replies

Hi, I am using virtex4 device for my designs. In timing analysis i found OBUF in V4 is 3.79ns which is a big obstacle for my design ....

Hi, I am using virtex4 device for my designs. In timing analysis i found OBUF in V4 is 3.79ns which is a big obstacle for my design . Is that a way , i can reduce this gate delay by giving some constraints. ie is to reduce the gate delay by tools .


Traversing hierarchy in UCF works for OBUF, but not IOBUF, please help

Started by Telenochek in comp.arch.fpga8 years ago 9 replies

Hi all, I have an SDRAM interface buried deep inside the hierarchy. I was able to instantiate OBUF for the control & address signals...

Hi all, I have an SDRAM interface buried deep inside the hierarchy. I was able to instantiate OBUF for the control & address signals and traverse the hierarchy from the UCF file to tie the signals to the FPGA pins. However, when I try to do something similar for the IOBUFs, I get an error of the type INFO:NgdBuild:889 - Pad net 'eight_chan_gen/u1/external_sdram/U1/ DQ ' is


different I/O buffers available inXilinx FPGA

Started by vlsi_learner in comp.arch.fpga12 years ago 9 replies

could anyone please explain me the difference between the buffers IBUF OBUF BUFGP BUFGDLL BUFT etc available in XILINX FPGA.

could anyone please explain me the difference between the buffers IBUF OBUF BUFGP BUFGDLL BUFT etc available in XILINX FPGA.


Xilinx DDR Register FDDRRSE

Started by Nick Suttora in comp.arch.fpga13 years ago

Is the Virtex II flip-flop primitive FDDRRSE limited in that its output can only connect to an I/O or obuf type primitve? The naming convention...

Is the Virtex II flip-flop primitive FDDRRSE limited in that its output can only connect to an I/O or obuf type primitve? The naming convention would imply that it can be used for internal connections to another CLB, but that doesn't appear to be the case.


WHAT SITUATION I NEED A BUFFER

Started by ZHI in comp.arch.fpga11 years ago 13 replies

I am a newer for FPGA. I am reading some vhdl codes of others. I find they often use some buffers in design, such as IBUF, OBUF,...

I am a newer for FPGA. I am reading some vhdl codes of others. I find they often use some buffers in design, such as IBUF, OBUF, FDCE, FDCE_1,etc.I have checked these buffer function but still not very sure the reason why these buffers put there. Is there anybody kindly tell me what situation we need a buffer? Or just give me some materials of it. I can check it by myself. Thanks


IBUF, IBUFG, OBUF

Started by rider in comp.arch.fpga14 years ago 1 reply

Hi all! I have a query regarding Xilinx FPGAs and the XST. In many documents relating FPGA designs, there are such statements as: BUFG...

Hi all! I have a query regarding Xilinx FPGAs and the XST. In many documents relating FPGA designs, there are such statements as: BUFG instance_name (.O (user_O), .I (user_I)); My question is that do we really need to instantiate BUFG, IBUFG etc in this manner? Isn't this automatically done by the tool(XST etc)? Lets say i am using a clk signal in my design. I LO...


DCM in Xilinx

Started by charles in comp.arch.fpga13 years ago 2 replies

I am doing a small experiment with DCM. I used the coregen to configure it to use a 100Mhz input clock, and output CLK0 and LOCKED. RST is...

I am doing a small experiment with DCM. I used the coregen to configure it to use a 100Mhz input clock, and output CLK0 and LOCKED. RST is also tied to a pushbutton RESET. Feedback 1x internal is configured, and so does the duty cycle correction. Then I instantiate the module in schematic, and tie all the port to inport and outport apprepriately without any IBUF,OBUF or BUFG primitives. ...


Xilinx OBUF attributes on Spartan3

Started by Marco in comp.arch.fpga11 years ago 12 replies

Hi, I'm trying to learn the way to work with output buffers and other features of the XC3S1000FG456 installed on my Analog Devices...

Hi, I'm trying to learn the way to work with output buffers and other features of the XC3S1000FG456 installed on my Analog Devices FPGA extender board. This board has 3 connectors placed in such a way to be able to connect it to a Blackfin DSP evaluation board, but it can work stand-alone as a normal Spartan3 evaluation board and that's the way I'm using it now. I wanted to push out a signa...


not replaced by logic error

Started by Stefano Trucco in comp.arch.fpga14 years ago 2 replies

Hi Thanks for reading this. I have a schematic (top level) design which has a data bus. This data bus has had IOB(63:0) and ...

Hi Thanks for reading this. I have a schematic (top level) design which has a data bus. This data bus has had IOB(63:0) and separate Ibuf(63:0) and OBUF(63:0) attached to an IO marker (bidirectional) and NOTHING else in the schematic. I get an error on synthesis that says: Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal


Question on using ODDR

Started by lioncat in comp.arch.fpga8 years ago 5 replies

Hello guys, I am working on a virtex 5 and trying to read out data from internal distributed ROM at 250MHz. Then in order to increase data rate,...

Hello guys, I am working on a virtex 5 and trying to read out data from internal distributed ROM at 250MHz. Then in order to increase data rate, I choose use ODDR which is followed by OBUF. But in the MAP I have this kind of errors at all the output of ODDR as following, "ERROR:Pack:1569 - The dual data rate register QPSK_wave/LOOP_DDR_A[6].ODDR_A failed to join an OLOGIC component as requi...


Xilinx ISE 7.1i / stuck down XCR3064 outputs

Started by Alex in comp.arch.fpga12 years ago 6 replies

Hi, I'm trying to use Xilinx ISE 7.1 on Linux to target an XCR3064. What seemed to happen was any pin configured as an output was stuck down...

Hi, I'm trying to use Xilinx ISE 7.1 on Linux to target an XCR3064. What seemed to happen was any pin configured as an output was stuck down to ground (able to draw 30mA) This happens even if the pins are internally connected (thru an obuf) to VCC or set to 1 in the design. Pins configured as input seems to work correctly.. high impedance and doing a sort of a floating latch behavior. I...


Proper/recommended method for driving clock out from FPGA

Started by bwil...@gmail.com in comp.arch.fpga10 years ago 3 replies

I've inherited a design at my new company where there are two source- synchronous interfaces at 80MHz SDR. On one interface a clock (tx_clk) is...

I've inherited a design at my new company where there are two source- synchronous interfaces at 80MHz SDR. On one interface a clock (tx_clk) is forwarded to the FPGA and on the other the clock (rx_clk) is forwarded from the FPGA. rx_clk is generated from taking tx_clk through an IBUF, BUFG, and finally an OBUF to the pad. These are single-ended LVCMOS25 clocks and the device is a Xilinx Vi...