EDK Microblaze project without OPB?

Started by JD Newcomb in comp.arch.fpga10 years ago 2 replies

Hi, all. Is it known to be possible to create a Microblaze system without the OPB? For example, say I have 1 MicroBlaze with 16KB of d&i...

Hi, all. Is it known to be possible to create a Microblaze system without the OPB? For example, say I have 1 MicroBlaze with 16KB of d&i BRAM, but I don't necessarily need the off-chip SDRAM or UART (or any OPB slave peripheral at all), so I don't include the OPB. And say it's part of a larger network to justify not needing the OPB for any peripherals. Currently, my 8.2 version has an...


EDK: OPB Question

Started by Anonymous in comp.arch.fpga11 years ago 1 reply

Hi all, I have two questions regarding the OPB usage. 1) why is it the microblaze connects to the IOPB port to the OPB bus when running from...

Hi all, I have two questions regarding the OPB usage. 1) why is it the microblaze connects to the IOPB port to the OPB bus when running from internal memory (BRAM) ? the program runs only from the ILMB isn't it? 2) PLB-OPB bridge , the PPC405 reference guide says that the PLB should be used for fast bus transactions and that the OPB is to be used for slower peripherals (GPIOs/UART etc.). My...


OPB To Wishbone Bridge

Started by Anonymous in comp.arch.fpga10 years ago 5 replies

Hi all, I am looking for an OPB to wishbone bridge to let OPB talk to my IP via wishbone in EDK. I have read some posts on OPB-> wishbone...

Hi all, I am looking for an OPB to wishbone bridge to let OPB talk to my IP via wishbone in EDK. I have read some posts on OPB-> wishbone wrapper (available at opencores.org). Had a look at the wrapper, which raises a couple of questions in my mind. Where is the OPB bus translation to wishbone bus taking place in this wrapper? How to use it in an environment where the IP is connected to the


OPB bus communication

Started by Nitesh in comp.arch.fpga12 years ago 4 replies

I have designed a small module usilng vhdl.I converted this module using IPIF and created an IP.Now I added this IP into my design as...

I have designed a small module usilng vhdl.I converted this module using IPIF and created an IP.Now I added this IP into my design as a master/slave module to the OPB bus.I have to inititate a transaction from my module to the OPB busi.e I want to send some data to the slave module connected to the opb bus. One thing I have noticed is that there is no M_Dbus as output of IPIF to OPB bus. ...


problem with Xilinx OPB to OPB bridge

Started by Anonymous in comp.arch.fpga12 years ago

hello all, I'm building a system with EDK 7.1 on a virtex4 using Xilinx IP and soft processor Microblaze .i'm using 2 OPB bus in my design the...

hello all, I'm building a system with EDK 7.1 on a virtex4 using Xilinx IP and soft processor Microblaze .i'm using 2 OPB bus in my design the first one is my mb_opb and there is another one (opb_2) who is link with mb_opb through an opb to opb bridge. My problem is there is no communication from my microblaze to my opb_2 ( no I/O from RS232 connect to opb_2). thanks for your answers.


Multichannel Opb Memory Controller question

Started by Marco T. in comp.arch.fpga11 years ago 9 replies

Hallo, I would develop a system based on opb multichannel memory sdram controller. I would connect Microblaze to the controller using xcl and...

Hallo, I would develop a system based on opb multichannel memory sdram controller. I would connect Microblaze to the controller using xcl and not opb bus. I would also connect an external microcontroller to sdram: I thought to create a custom opb master peripheral and connect it to opb bus. The opb bus will have a master (the external micro) and a slave (the sdram). Is it reliable? ...


OPB versus PLB

Started by Frank van Eijkelenburg in comp.arch.fpga13 years ago 1 reply
OPB

Could somebody explain me why the OPB bus is used for "slow" peripheral and the PLB bus for "fast" peripherals? I have a small design with both...

Could somebody explain me why the OPB bus is used for "slow" peripheral and the PLB bus for "fast" peripherals? I have a small design with both an OPB and PLB bus and both are running at 100 MHz. Of course there is a delay when access devices at the OPB bus from a PowerPC (OPB2PLB bridge). But is this the only delay or are there more (like burst supports etc.). TIA, Frank


OPB write actions

Started by Frank in comp.arch.fpga14 years ago 3 replies

Hi, I've succesfully build a microblaze system with external interrupt and my own IP core (using the opb slave template in the EDK). The...

Hi, I've succesfully build a microblaze system with external interrupt and my own IP core (using the opb slave template in the EDK). The interrupt is connected to a dip-switch. In the ISR I'm writing some data to my own IP core (which is an OPB slave). My OPB slave is reading some other dip-switches and put the result to some LEDs (yes I'm using an evaluation board ;). So far everything is...


EDK 6.1 vs 3.2 and OPB Bus resets

Started by Carlos Villalpando in comp.arch.fpga13 years ago 2 replies

Hey all. I'm having a problem with transitioning to EDK 6.1 with a custom OPB peripheral. I started out with EDK 3.2/ISE 5.2 with a custom...

Hey all. I'm having a problem with transitioning to EDK 6.1 with a custom OPB peripheral. I started out with EDK 3.2/ISE 5.2 with a custom OPB peripheral in a Microblaze system on a V2 with a well populated OPB bus. That system works fine, but we have new hardware and need to transistion. I'm moving to EDK 6.1/ISE 6.1 with a V2Pro/PPC system with the same OPB peripheral. The new s...


chipscope opb monitor

Started by Frank van Eijkelenburg in comp.arch.fpga11 years ago 5 replies

I try to use the opb/iba unit of chipscope to monitor the opb bus within a simple edk design. I took the chipscope lab example as start point. I...

I try to use the opb/iba unit of chipscope to monitor the opb bus within a simple edk design. I took the chipscope lab example as start point. I am able to see the OPB signals in chipscope, but I can not set a trigger point. For example, I want to trigger at a certain address 0xFFFFXXXX. If I wait for the triggercondition, the behaviour is the same if no condition is set (like the immedi...


Loading the design from Compact Flash...

Started by Xesium in comp.arch.fpga9 years ago 6 replies

Hi everybody, It's been a while I'm struggling with ML310 board to have my design loaded from compact flash to the Virtex II-pro FPGA on the...

Hi everybody, It's been a while I'm struggling with ML310 board to have my design loaded from compact flash to the Virtex II-pro FPGA on the board. I'm generating system.ace file using iMPACT and program the compact flash using a card reader. In my design I have a Microblaze with an OPB timer, OPB SysAce controller and OPB uart-lite, I have some more controllers connected to OPB which I thin...


Question about Xilinx OPB/PCI bridge

Started by Riz in comp.arch.fpga12 years ago

Hi, I am new using Xilinx EDK. The version I'm using is 6.3. I'd like to access OPB bus from PCI side. I'm Xilinx OPB/PCI bridge v3 in a...

Hi, I am new using Xilinx EDK. The version I'm using is 6.3. I'd like to access OPB bus from PCI side. I'm Xilinx OPB/PCI bridge v3 in a project where I'm using custom board. Linux and Windows are able to recognize the PCI bridge and does allocate resources but unable to access to the device on the OPB bus. Please have a look at my mhs file, and advise me if I have done something wron...


Microblaze PLB vs. OPB busses

Started by Eric Smith in comp.arch.fpga10 years ago 1 reply

Now that Microblaze has support for either PLB or OPB, what are the advantages and disadvantages of PLB? I started looking at the...

Now that Microblaze has support for either PLB or OPB, what are the advantages and disadvantages of PLB? I started looking at the PLB specification, but I don't yet understand it well enough to have any feel for how it compares to OPB, or why it might be preferred. Thanks, Eric


OPB Master Peripheral

Started by chakra in comp.arch.fpga10 years ago 3 replies

Hello all, I am working on a project, in which am trying to make OV7660 camera protoboard to talk to ML300 Xilinx FPGA board.I have a general...

Hello all, I am working on a project, in which am trying to make OV7660 camera protoboard to talk to ML300 Xilinx FPGA board.I have a general question regarding OPB bus. Here is the set up: I am building a OPB Master peripheral which directly talks to camera (8 data, vsync, Href and Pixclk) via GPIO pins on the ML300 board. The same master peripheral talks to OPB DDR SDRAM which is a sla...


16-bit sdram and 32-bit opb bus

Started by Frank in comp.arch.fpga14 years ago 1 reply

Is it possible to use the opb sdram controller with a 32-bits opb bus to a microblaze one side and a 16-bits sdram to the other side? What if I...

Is it possible to use the opb sdram controller with a 32-bits opb bus to a microblaze one side and a 16-bits sdram to the other side? What if I do a 32-bits access to sdram. Will the controller convert this automatically in two 16-bits cycles? The datasheet of the opb sdram controller says: "Since the sdram will always be accessed to provide data the width of the OPB bus, ...". So it looks li...


Xilinx EDK: Slow OPB write speeds

Started by Anonymous in comp.arch.fpga10 years ago 10 replies

Hi All, I've a simple peripheral with an OPB interface. In a nutshell I've been getting some very slow write speeds over the OPB and wanted to...

Hi All, I've a simple peripheral with an OPB interface. In a nutshell I've been getting some very slow write speeds over the OPB and wanted to see if this was normal, or if there was anything I can do to speed things up. I've tried a number of configurations. Trying PPC and microblaze based systems. Using the OPB_IPIF and connecting directly to the bus. The results are: Virtex2Pro + P...


microblaze with opb, brams?

Started by Jack in comp.arch.fpga12 years ago 1 reply

hi all I am wondering if it is feasible for OPB to connect microblaze and BRAMS. For instance, OPB connects one microblaze and 2 64KB BRAMS...

hi all I am wondering if it is feasible for OPB to connect microblaze and BRAMS. For instance, OPB connects one microblaze and 2 64KB BRAMS (with different address map). Each BRAM is instruction/data dual port. So programmer may consider the system has 128 KB memory space. How do you find this scheme? Are there any other things to consider? thankyou for reply


Question about initializing on-chip block mem in XPS?

Started by cathy in comp.arch.fpga11 years ago 7 replies

Hello, if my system is organized as the following ---------Microblaze-----lmb-----8k BRAM | ...

Hello, if my system is organized as the following ---------Microblaze-----lmb-----8k BRAM | Opb Bus | 64k BRAM-----opb bus-----customized circuit I initialized my opb bram with the following sentence. float *y, *z; y=(float *)(XPAR_OPB_BRAM_IF_CNTLR_1_BASEADDR+YBaseAddr); z=(float *)...


Example using a custom OPB slave core with and interrupt

Started by Jeremy in comp.arch.fpga13 years ago

Hello, I have been exploring the microblaze for about 2 weeks now and have gotten to the point where I have created a simple OPB slave...

Hello, I have been exploring the microblaze for about 2 weeks now and have gotten to the point where I have created a simple OPB slave device that consists of 4 32-bit registers that contain hard coded values and a pushbutton input that generates an interrupt. There is only one single interrupt so I have connected it directly to the Mblaze without the use of an OPB Intc at this point. T...


OPB monitor error

Started by Anonymous in comp.arch.fpga11 years ago 7 replies

Hi all, I'm currently verifying an OPB master i/f using IBM's OPB monitor. I'm currently getting an error 1.11.3, which says I didn't...

Hi all, I'm currently verifying an OPB master i/f using IBM's OPB monitor. I'm currently getting an error 1.11.3, which says I didn't increment the ABus correctly during seqAddr bus access. The particular case I'm looking at is this: ABus = 32'h00000E69, and BE = 4'b0111, using sequential address, byte-enable transfer, and xfer_size is "byte." The slave I wrote into is a full-word device t...