Picobalze in the FPGA

Started by Himlam8484 in comp.arch.fpga15 years ago 10 replies

Hi people, i am a new person in the FPGA field. I have just made something with IC from Xilinx( just make a FPGA'sboard at home). I know it...

Hi people, i am a new person in the FPGA field. I have just made something with IC from Xilinx( just make a FPGA'sboard at home). I know it worked well when i check it with some program.I started to learn to control it.It is said that There is a processor inside FPGA called Picoblaze. I try to program for it, but i have no following thing. I can program with the C software, then use a ...


flash controller

Started by superwolfish in comp.arch.fpga12 years ago 1 reply

Hi everybody, i need some Mbits of flash storage, and i need them to be controlled from a fpga. I'm using Xilinx tools. Is the memory...

Hi everybody, i need some Mbits of flash storage, and i need them to be controlled from a fpga. I'm using Xilinx tools. Is the memory controller MIG from "IP Core generator" suitable to control NOR FLASH memory? I only see the options DDR ans DDR2 when configuring MIG. I'm not using microblaze nor picoblaze. And i need to read and to write the flash at very different times, that is, not...


Lattice "Open IP" license is GPL-compatible?

Started by Anonymous in comp.arch.fpga14 years ago 4 replies

I'm working on a new project using some code from opencores for my thesis research. I'd love to use a nice, high-quality tiny-fsm like picoblaze...

I'm working on a new project using some code from opencores for my thesis research. I'd love to use a nice, high-quality tiny-fsm like picoblaze or the lattice semi micro8. However, I'm worried about licensing issues, as I'd also like to be able to use the opencores IP and release the whole thing under the GPL. Does anyone know / have a strong opinion on whether or not the Lattice Open IP li...


spartan3 picoblaze how to make .bmm file work

Started by Bart van Deenen in comp.arch.fpga14 years ago 5 replies

I'm a newbie in fpga design, and am really struggling to create a bmm file that works. I am using an Spartan-3A starter kit, with ISE 9.2.0i on...

I'm a newbie in fpga design, and am really struggling to create a bmm file that works. I am using an Spartan-3A starter kit, with ISE 9.2.0i on Linux. I am working with the dna reader project, and am capable of downloading the design, as well as modifying the assembly program (dna_ctrl.psm), and updating it via the whole "implement design" route. I'm really interested in the direct modifica...


spartan 3an lcd application doesn't work

Started by Anonymous in comp.arch.fpga13 years ago

I have wrote the following code in verilog (using the reading_dna.vhd file on the xilinx site) to run the picoblaze code that I found online. I...

I have wrote the following code in verilog (using the reading_dna.vhd file on the xilinx site) to run the picoblaze code that I found online. I synthesized the code, produced, and send a .bit using ISE 10.1 to the Spartan 3an, however, the LCD screen doesn't display anything. Can someone run this and check if there is something wrong ? module lcdtest(lcd_d, lcd_rs, lcd_rw, ...


Free Seminar

Started by John Adair in comp.arch.fpga17 years ago 1 reply

Apologies to those who don't like ads but this free and has no strings attached. It is biased to MicroBlaze and PicoBlaze on the basis of that...

Apologies to those who don't like ads but this free and has no strings attached. It is biased to MicroBlaze and PicoBlaze on the basis of that is what we do most. If you are in our locality please let us know if you would like to attend. Link is http://www.enterpoint.co.uk/seminar/microblaze_intro.html John Adair Enterpoint Ltd. http://www.enterpoint.co.uk This message is the persona...


async fifo design

Started by Michael Dreschmann in comp.arch.fpga16 years ago 9 replies

Hi, I'm designing an "On Chip Network" System consisting of one network master and several network interfaces. Every interface is connected...

Hi, I'm designing an "On Chip Network" System consisting of one network master and several network interfaces. Every interface is connected to a prozessor (picoblaze) which can transmit and receive data onto/from the network. Now I'd like to have two completely independent clocks on the network and on the prozessor bus site. In the network interface I use two fifos (rx and tx) implemented...


Ethernet : MAC vs PHY

Started by Tom Vrankar in comp.arch.fpga16 years ago 2 replies

I have a 10BASE-T MAC/stack design (using PicoBlaze, BTW) which I'm trying to bring up on the Avnet/Memec S3MB Spartan3 1500-based board. I've got...

I have a 10BASE-T MAC/stack design (using PicoBlaze, BTW) which I'm trying to bring up on the Avnet/Memec S3MB Spartan3 1500-based board. I've got the board connected to a PC, nothing else, running "ping" and Ethereal. The S3MB board pins-out the Rx and Tx lines the reverse of the PC, so I am using a straight-thru cable. My design receives ARP and ICMP ECHO frames from the Broadcom BCM5221 (jumper...


picoblaze assembler : kcpsm3.exe and wine/linux

Started by Anonymous in comp.arch.fpga15 years ago 4 replies

Hi groups, is there something special to get kcpsm3 running on linux/wine ? my wine conf seems ok (FileZila win edition is running...

Hi groups, is there something special to get kcpsm3 running on linux/wine ? my wine conf seems ok (FileZila win edition is running fine) but KCPSM3.EXE faills (Unhandled page fault on read access to 0xffffffff...) any idea,


FPGA Processor for Signal Processing ?

Started by Anonymous in comp.arch.fpga13 years ago 3 replies

You find at the web and in books implementations of processors for FPGA =B4s and also processors like Picoblaze and Microblaze from firms...

You find at the web and in books implementations of processors for FPGA =B4s and also processors like Picoblaze and Microblaze from firms like Xilinx. Are there also implementations of processors special designed for signal processing that realize things like FFT for example ? Thanks for help


What's a good book on FPGA CPU design?

Started by Pratip Mukherjee in comp.arch.fpga18 years ago 3 replies

Hi, Is there a good book on FPGA CPU design which starts with a simple cpu, like Xilinx PicoBlaze, and takes the user through different aspect...

Hi, Is there a good book on FPGA CPU design which starts with a simple cpu, like Xilinx PicoBlaze, and takes the user through different aspect of cpu design like instruction set design, pipelining, etc., etc, at the same time keeping the focus on actual implementaion in a FPGA and not on theoritical discussions? Am I asking for too much? Thanks. Pratip Mukherjee.


using mpmc ddr2 controller with an other processor

Started by rpon...@gmail.com in comp.arch.fpga13 years ago 1 reply

hi groups ! what is the best route in order to use an edk generated mpmc ddr2 controller with a custom processor (not microblaze, but gaisler...

hi groups ! what is the best route in order to use an edk generated mpmc ddr2 controller with a custom processor (not microblaze, but gaisler leon3 or even picoblaze ; this is for edu. purpose...) ? I have a copy the ddr2_sdram_wrapper.ngc and clock_generator_0_wrapper.ngc files (these are good, tested with a microblaze design). I read xilinx mpmc.pdf but I am lost ... I think I need ...


using spartan 3E starter kit for CAN bus probe ?

Started by Anonymous in comp.arch.fpga15 years ago

Hi experts ! in your opinion, is it possible to build a CAN field bus probe (simple app. for edu. ; needs only to display Id and data , no...

Hi experts ! in your opinion, is it possible to build a CAN field bus probe (simple app. for edu. ; needs only to display Id and data , no CANopen objects) with the spartan 3E starter kit + ISE and EDK ? 1) Does is have enough bram ? and mips ? ... ? 2) The minimalistic system should be build around a picoblaze soft processor for data display to lcd and www.opencores.org CAN controler ...


small, free simple state machine processor suggestions?

Started by Anonymous in comp.arch.fpga15 years ago 5 replies

Has anyone found or could recommend a small(ish) processor for more complex state machine tasks that is: 1. ~1000 LUTs or so (smaller is...

Has anyone found or could recommend a small(ish) processor for more complex state machine tasks that is: 1. ~1000 LUTs or so (smaller is better) 2. available under a free license (say, GPL, LPGL, BSD) 3. available in vhdl? Ideally something like picoblaze would probably do what I want, except that it's not under any of the available licenses, and pacoblaze is vhdl (and potentially an IP...


JTAG Loader tools won't execute

Started by mludwig in comp.arch.fpga14 years ago 5 replies

I just wanted to try the JTAG Loader tools provided with PicoBlaze and I cannot run neither hex2svf.exe, nor hex2svfsetup.exe. I get "The system...

I just wanted to try the JTAG Loader tools provided with PicoBlaze and I cannot run neither hex2svf.exe, nor hex2svfsetup.exe. I get "The system cannot execute the specified program" message in the Windows XP Command Prompt. Am I missing something here? Has anybody been able to run these tools and program the instruction ROM via JTAG? Thanks,


Data Muxing on Spartan3 using the embedded carry chain

Started by Anonymous in comp.arch.fpga15 years ago 1 reply

Hi All, Does anyone know how to use the embedded carry chain for data muxing. The Picoblaze docs state that it can use the MUXCY for this. I am...

Hi All, Does anyone know how to use the embedded carry chain for data muxing. The Picoblaze docs state that it can use the MUXCY for this. I am not sure how to use it for data muxing, if anyone knows, your help will be greatly appreciated. Thanks in advance Sudhir


State machine with stack to implement "subroutines"

Started by Wojciech Zabolotny in comp.arch.fpga14 years ago 8 replies

Hi All, Playing with the Spartan 3E Starter Kit reference designs, I've found the following "Exercise" in the "Initial Design - LCD Display...

Hi All, Playing with the Spartan 3E Starter Kit reference designs, I've found the following "Exercise" in the "Initial Design - LCD Display Control). Exercise: Implement a hardware state machine which can perform the LCD initialisation sequence. Compare the size of your implementation with the 96 slices required to implement a PicoBlaze processor. Trying to implement a required state ...


IP Protection of code block in Xilinx FPGA?

Started by Paul Urbanus in comp.arch.fpga16 years ago 4 replies

I have an FPGA design where the VHDL source code is a deliverable item to the customer. One of the blocks in the FPGA must be protected so that...

I have an FPGA design where the VHDL source code is a deliverable item to the customer. One of the blocks in the FPGA must be protected so that the customer can't see the source and modify it. The device is a Virtex2-Pro. I could obfuscate the VHDL identifiers, then generate a netlist, but that doesn't seem to be very strong protection. I also have a picoblaze processor in the design,...