Using Quarus to create SVF files?

Started by Anonymous in comp.arch.fpga14 years ago

Is there a way to generate SVF files in Quartus II? If not, is there a way to convert JAM files to SVF? TIA Petter -- A: Because it...

Is there a way to generate SVF files in Quartus II? If not, is there a way to convert JAM files to SVF? TIA Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?


Quartus II 3.0 Release & Web Edition Download Links

Started by Subroto Datta in comp.arch.fpga14 years ago 6 replies

Quartus II software version 3.0 is now available on the PC, Solaris, Red Hat Linux, and HP-UX operating systems. Customer CD shipments will be...

Quartus II software version 3.0 is now available on the PC, Solaris, Red Hat Linux, and HP-UX operating systems. Customer CD shipments will be made from July 11 - July 21. The Web Edition is available for download now. Learn about the new features in Quartus II version 3.0 at For general Quartus II softw


Problem with user defined logicinterface in Nios

Started by Thorsten Klatt in comp.arch.fpga14 years ago

Hi, I am using Quartus 2.2 SP2 with Nios 3.0 I have fit my logic with the SOPC into the Niosstructure and generating and compiling of this...

Hi, I am using Quartus 2.2 SP2 with Nios 3.0 I have fit my logic with the SOPC into the Niosstructure and generating and compiling of this is fine. I am testing on a stratix devel. board. Programming of the fpga works out fine too. The problem is, that no programm runs on the nios. (i.e. hello_world) The srec file is downloaded to the chip and then just the terminal appears. (nr -r hell...


Re: Rant mode ON

Started by John in comp.arch.fpga14 years ago 10 replies

Hey Rickman, In article , spamgoeshere4@yahoo.com says... > I need to vent a little steam. So at risk of making myself look stupid > ...

Hey Rickman, In article , spamgoeshere4@yahoo.com says... > I need to vent a little steam. So at risk of making myself look stupid > (or more stupid) I will do it here. > > I have been trying to get the Quartus 3.0 software and a license since > last Thursday. I tried three times over the weekend to download it, but > the slow modem link I have to use w


Synplify and then Quartus

Started by Prashant in comp.arch.fpga14 years ago 1 reply

Hi, I have been using Quartus II 2.0 for all my synthesis and fitting needs for the APEX20KE device I have on my prototype board. I hear that...

Hi, I have been using Quartus II 2.0 for all my synthesis and fitting needs for the APEX20KE device I have on my prototype board. I hear that Quartus is not an efficient synthesizer compared to Synplicity's Synplify. Now, I have had trouble trying to fit my design on the FPGA and I have tried various methods to achieve successful fits (Logiclock, design change, etc.). Would there be a d...


Quartus VHDL problem with aggregate and type cast

Started by rickman in comp.arch.fpga14 years ago 3 replies

Here is some code showing a problem I am having with Quartus. Seems using a type cast with an aggregate throws it all off. This is just...

Here is some code showing a problem I am having with Quartus. Seems using a type cast with an aggregate throws it all off. This is just a simple test case which uses a 16 bit bidir bus to write to an 8 bit register and read it back. -- VHDL created by Rick Collins Library ieee; Use ieee.std_logic_1164.all; Use ieee.numeric_std.all; ENTITY Test1 is PORT ( Data : INOUT STD_LOG...


Limitations of Quartus II V3.0 Web

Started by Chris in comp.arch.fpga14 years ago 4 replies

Hi guys, I'm trying to simulate a block-based design with Altera's Quartus II V3.0 Web version, however I cannot seem to simulate beyond...

Hi guys, I'm trying to simulate a block-based design with Altera's Quartus II V3.0 Web version, however I cannot seem to simulate beyond 100ns irrespective of what end points I set for the default and for the current project. I've also tried editing the vector waveform file timing parameters after generation and Quartus disregards these and ends the simualtion at 100ns. It seems far to...


Performance of STAPL player on embedded systems

Started by Rienk van der Scheer in comp.arch.fpga14 years ago

I there anyone who implemented Altera's STAPL bytecode player on an embedded system (say 16-bit microcontroller) to program large FPGAs and...

I there anyone who implemented Altera's STAPL bytecode player on an embedded system (say 16-bit microcontroller) to program large FPGAs and PROMs? It seems that especially the bitshift operations are programmed very ineffiently, resulting in a performance worse than needed. The .jbc files generated by Quartus 3 are reasonable efficient for FPGAs because they only execute a single DRSCA...


altera latch synthesis

Started by Andrea in comp.arch.fpga14 years ago 5 replies

Hi all, I'm working with Quartus II 2.2 sp2 and my target fpga is APEX20KE. I have described a latch in my VHDL code with an enable signal,...

Hi all, I'm working with Quartus II 2.2 sp2 and my target fpga is APEX20KE. I have described a latch in my VHDL code with an enable signal, something like this library ieee; use ieee.std_logic_1164.all; entity my_lat is port (d : in std_logic; en : in std_logic; clk : in std_logic; q : out std_logic); end my_lat; architecture rtl of my_lat is ...


system simulation and verification methods (NIOS)

Started by J-Wing in comp.arch.fpga14 years ago 1 reply

what ways and approaches are there to do system level simulation? i have a nios system module and a user logic which have been...

what ways and approaches are there to do system level simulation? i have a nios system module and a user logic which have been connected together via the avalon bus. can simulation be done using quartus II?


Altera's Quartus II "smart compilation" feature killed my design?

Started by enq_semi in comp.arch.fpga14 years ago 12 replies

Hi, there, I have a design contains 12K logic cells and 300K bit memories and runs at 5MHz. I compiled it for an EP20K1500 device and it...

Hi, there, I have a design contains 12K logic cells and 300K bit memories and runs at 5MHz. I compiled it for an EP20K1500 device and it worked (tested on FPGA). Then I wanted to switch 8 output bits from pin location AF1, AF2, AF3, AF4, G4, G5, G6 and H2 to DAC0 pins (AE1, AD1 -- AD6 and AC6). I had the smart compilation option turned on when I successfully compiled and tested the de...


What CPU for Quartus II?

Started by Anonymous in comp.arch.fpga14 years ago 1 reply

Hi all, I wonder if anyone has benchmarked contemporary high-end desktop processors -- Athlon, Opteron and P4/Xeon basically -- for which...

Hi all, I wonder if anyone has benchmarked contemporary high-end desktop processors -- Athlon, Opteron and P4/Xeon basically -- for which is better to do Quartus II synthesis? -hpa -- at work, in private! If you send me mail in HTML format I will assume it's spam. "Unix gives you enough rope to shoot yourself in the foot." Architectures needed:


Quartus internal synthesis more verbose?

Started by Anonymous in comp.arch.fpga14 years ago

Hi I am using Quartus internal synthesis (Quartus3.0). Is there a way to switch it to a little bit more verbose output (i.e. there are nearly...

Hi I am using Quartus internal synthesis (Quartus3.0). Is there a way to switch it to a little bit more verbose output (i.e. there are nearly no warnings if there are flaws in your code, like problematic type conversions. I like the output of Leonardo much better Roman


ByteblasterMV and QuartusII 3.0

Started by Christian Riesch in comp.arch.fpga14 years ago

I have a homebuilt Byteblaster MV which works fine with Altera Max+PlusII 10.2. With Quartus II 3.0 SP1 "Auto Detect" of the devices in the JTAG...

I have a homebuilt Byteblaster MV which works fine with Altera Max+PlusII 10.2. With Quartus II 3.0 SP1 "Auto Detect" of the devices in the JTAG chain works, but when I try to program it reports Info: Configuring device index 2 Error: Can't configure device. Expected JTAG ID code 0x110500DD for device 2, but found JTAG ID code 0x00000000. Error: Unexpected error in JTAG server -- error cod...


Quartus II 2.2 smart compile ignoring .mif

Started by Anonymous in comp.arch.fpga14 years ago

I'm having a very odd problem... Quartus II (2.2) has started ignoring .mif file changes on me when doing "smart compile", which requires me to...

I'm having a very odd problem... Quartus II (2.2) has started ignoring .mif file changes on me when doing "smart compile", which requires me to sit for 20 minutes and recompile the whole design for a simple memory change. The really weird part is that this is new behaviour -- I have one project on which this works beautifully and it was a major assistance debugging that design, but on a di...


Using LUTs for array of coefficients

Started by Bob in comp.arch.fpga14 years ago 7 replies

Hello again, I have an array of 16 10 bit coefficients, and I would like to store these in LUT on an FPGA instead of Flops. Can I do this in...

Hello again, I have an array of 16 10 bit coefficients, and I would like to store these in LUT on an FPGA instead of Flops. Can I do this in Xilinx and Altera devices by selecting various options say on Quartus, or can I switch on any synthesis switches or do I have to change my VHDL. Any ideas as always is greatly appreciated. Thanks Bob


Quartus Usability Feedback

Started by Subroto Datta in comp.arch.fpga14 years ago

Quartus II 4.0 contains several improvements to make it easier to use, for Max+Plus II users. We are interested in testing these usability...

Quartus II 4.0 contains several improvements to make it easier to use, for Max+Plus II users. We are interested in testing these usability changes on existing Max+Plus II users, who have had limited exposure to Quartus II. The only requirement is that the respondents be in the Bay area and be willing to visit the Altera Office in San Jose (near Montague and First Street). It should take no mo...


Strange synthesis behavior from Quartus II 2.2

Started by Prashant in comp.arch.fpga14 years ago 4 replies

Hi, I have a design that was compiled in Quartus II 2.0 (SP2) and used 22,000 logic elements on the APEX20K1500E device. I compiled the...

Hi, I have a design that was compiled in Quartus II 2.0 (SP2) and used 22,000 logic elements on the APEX20K1500E device. I compiled the same design in Quartus II 2.2 (SP2) and it takes 42,000 logic elements !! Has anyone seen such strange behavior with Quartus II 2.2 ? If so, how is this bug fixed ? Thanks, Prashant PS : Also, in the summary report, Quartus II 2.0 shows 85/493 pins ...


NIOS and OCI

Started by Jerry in comp.arch.fpga14 years ago 5 replies

This is from memory since work doesn't have access to newsgroups so here goes. We have a Stratrix development board with the NIOS software...

This is from memory since work doesn't have access to newsgroups so here goes. We have a Stratrix development board with the NIOS software package. Along with that is FS2 debugger. I have worked through the enclosed tutorials both the HW and SW. All was well and the debugger worked fine. I then wanted to add my own hardware into the PGA. I created a new project popped open Quartus 3.0 an...


ByteBlaster with USB<->PP adapter?

Started by Anonymous in comp.arch.fpga14 years ago 3 replies

Hi all, Does anyone know if Altera Quartus II (3.0+) will let me use a parallel port to USB adapter? I just got a new machine, in part so...

Hi all, Does anyone know if Altera Quartus II (3.0+) will let me use a parallel port to USB adapter? I just got a new machine, in part so I could upgrade to 3.0 from 2.2 (and in part so everything would go faster), but it doesn't have a parallel port! I basically have three options: waste the only PCI slot in the machine for a parallel port card, use a USB adapter, or special-order a man...