Looking for recent Altera Quartus Verilog synthesis experience

Started by John Providenza in comp.arch.fpga18 years ago 3 replies

I'm looking at doing a design with Apex-II parts and will probably need to use the Verilog synthesizer that comes with Quartus. My last...

I'm looking at doing a design with Apex-II parts and will probably need to use the Verilog synthesizer that comes with Quartus. My last experience (multiple years ago) was very unpleasant - lots of synthesis bugs. Has this gotten better? My experience with XST synthesis recently has been pretty good, so I'm debating about sticking with Xilinx for this next project or jumping to Alte...


High-performance workstation

Started by DK in comp.arch.fpga18 years ago 4 replies

Hi, could somebody suggest hi-performance workstation I can use to compile my designs in a fastest possible way? I use Altera Quartus III...

Hi, could somebody suggest hi-performance workstation I can use to compile my designs in a fastest possible way? I use Altera Quartus III and EP1C12Q240 device. It 90% full with most of the memory used. My Athlon XP 1800+ on ASUS A7V266-C motherboard with 512M of RAM takes 8/23 minutes to compile/fit. I did try dual Xeon 2200 on TYAN MB and it did only 5% faster.. Did somebody try A...


Quartus II tutorial vs the real world

Started by pjjones in comp.arch.fpga18 years ago 7 replies

I'm working with a Stratix EP1S40 evaluation baord, after going through the tutorial successfully (there is no mention of pin assignments in the...

I'm working with a Stratix EP1S40 evaluation baord, after going through the tutorial successfully (there is no mention of pin assignments in the tutorial, that would have been a nice touch i think), I tried a similar nios processor design from scratch to no avail. What I've figured out is this: if I begin with the given tutorial files, delete everything on the block diagram, and make a mi...


Reusing code (Altera Quartus II 3.0)

Started by Panic in comp.arch.fpga18 years ago 2 replies

Hi I am a relative "n00b" with regard to FPGA-programming, but I'm currently working on a Rijndael-implementation on a APEX1A dev.board. And...

Hi I am a relative "n00b" with regard to FPGA-programming, but I'm currently working on a Rijndael-implementation on a APEX1A dev.board. And I have run into some problems. I want to put my top-level design together from several smaller building blocks, that I want to design, compile, simulate and "forget". So when I need them later on, I'd like to simply import them into my design. T...


synplify vqm not able to fit in Quartus

Started by Bob in comp.arch.fpga18 years ago 7 replies

Hi, I am trying to fit this particular design. I run Synplify Pro to map the device. In Synplify, with mapping logic to atoms turned on, the...

Hi, I am trying to fit this particular design. I run Synplify Pro to map the device. In Synplify, with mapping logic to atoms turned on, the design won't fit so I disable mapping logic to atoms and can get the design to fit (63 % of device) onto the device....see log file from synplify below. However, when I try to place and route the device in Quartus III, it cannot fit. Quartus use...


Quartus, JTAG, Programming Hardware

Started by Christian Kramer in comp.arch.fpga18 years ago 2 replies

Hi! I am using three CPLDs in my design. Each one has its own JTAG connector, an I have three Byteblasters connected to LPT1-LPT3 on my...

Hi! I am using three CPLDs in my design. Each one has its own JTAG connector, an I have three Byteblasters connected to LPT1-LPT3 on my PC. Is there any way to save the configuration, which hardware is to be used for programming in the .cdf-file for each design? When I reopen the .cdf-files the programming-hardware is always the last one used - even if it was used in an different proj...


Quartus II simulation question.

Started by Christos in comp.arch.fpga18 years ago 3 replies

Hi all, In the vector waveform file that I am creating to enter the inputs for my simulation I can also enter the outputs and the registers...

Hi all, In the vector waveform file that I am creating to enter the inputs for my simulation I can also enter the outputs and the registers that I would like to be recorded. There using the node finder I can enter some combinatorial signals that I would like to observe. But after the simulation those signals have been omitted and the warning has been given : "Warning: Ignored node in vec...


Quartus help with package declaration

Started by Pratip Mukherjee in comp.arch.fpga18 years ago 1 reply

Hi, Using QuartusII 3.0, I have a VHDL file with a package declaration. From a VHDL file in a project I can see the declarations in the...

Hi, Using QuartusII 3.0, I have a VHDL file with a package declaration. From a VHDL file in a project I can see the declarations in the pacakage by using use work. .all; But from another VHDL file in the same project, the same 'use' line gives the following error: Error: VHDL Use Clause error at .vhd( ): design library work does not contain primary unit


Quartus 2.2, SOPC builder and leonardo

Started by Mancini Stephane in comp.arch.fpga18 years ago 5 replies

Hi all, I'm wondering how to synthesize the VHDL from SOPC Builder of quartus 2.2 with Leonardo. Indeed, I would like to perform a synthesis...

Hi all, I'm wondering how to synthesize the VHDL from SOPC Builder of quartus 2.2 with Leonardo. Indeed, I would like to perform a synthesis separated from the Quartus P&R for a course (I have a limited time and doing the both is far too long). The idea is to provide students an already synthesized system : they just have to complete some peripherals so I can pre-synthesize the whole system ...


EPC16 will not Flash Program

Started by Steven in comp.arch.fpga18 years ago 1 reply

I have a design with a JTAG chain consisting of APEXII, EPC16UC88, MERCURY, EPC16UC88. I have built the design 3 previous times and been able...

I have a design with a JTAG chain consisting of APEXII, EPC16UC88, MERCURY, EPC16UC88. I have built the design 3 previous times and been able to program my boards, no problems. Now I have 3 boards, one works fine, one will not accept a .POF file into the second EPC16 part, and the third will not accept a .POF into either of the EPC16 parts. What happens is Quartus starts erasing the p...


Running Quartus II on ReadHat Linux 9.0

Started by linux user in comp.arch.fpga18 years ago 4 replies

Hello: Altera Quartus II version 3.0 runs fine on RedHat Linux 9.0. If you are interested, I will post here how to do this. ----

Hello: Altera Quartus II version 3.0 runs fine on RedHat Linux 9.0. If you are interested, I will post here how to do this. ----


Running Quartus II on ReadHat Linux 9.0

Started by linux user in comp.arch.fpga18 years ago 18 replies

October 18, 2003 The procedure is posted at: If you experience any problem, (I may I missed something) post a message here.

October 18, 2003 The procedure is posted at: If you experience any problem, (I may I missed something) post a message here.


Several Quartus II 3.0 questions

Started by Panic in comp.arch.fpga18 years ago 4 replies

I'm a student working an a Altera EPXA1F484C1 FPGA, and I'm having some problems I hope someone can help me with. 1. Is there a way to tell...

I'm a student working an a Altera EPXA1F484C1 FPGA, and I'm having some problems I hope someone can help me with. 1. Is there a way to tell Quartus that the project I'm compiling is ment as a "internal" building block, meaning that the pins isn't actual device pins, but "internal pins"? I'm wondering since I have several "internal blocks" with 128 bits in and out, and Quartus stops my com...


Sort of Running Quartus II on SuSE Linux 8.1

Started by Mike Treseler in comp.arch.fpga18 years ago 5 replies

Quartus II on SuSE Linux 8.1 -- Installs fine. -- quartus -g comes up fine. -- Loads an existing project fine. -- Recompiles a...

Quartus II on SuSE Linux 8.1 -- Installs fine. -- quartus -g comes up fine. -- Loads an existing project fine. -- Recompiles a windows precompiled project fine -- Can't compile a new project itself. Tries for a while then says "Error: Current module quartus_map ended unexpectedly". -- Mike Treseler


Strange error in Quartus II 3.0

Started by Panic in comp.arch.fpga18 years ago 6 replies

After searching for the source of an error for quite a long time, I've decided that I need some help, and once again you guys drew the...

After searching for the source of an error for quite a long time, I've decided that I need some help, and once again you guys drew the shortest straw ;-) I have a 8 bit DFF with output q[7..0]. This feeds the net dff_inst23_out[7..0]. (The reason this net is given this name, was to see if the error actually was located where I thought it was, since the original error pointed to some temp n...


NIOS simulation with modelsim -> strange behaviour

Started by Mancini Stephane in comp.arch.fpga18 years ago

Hi, I would like to simulate a NIOS system with modelsim but I have very strange results : it seems that the external SRAM (for the Nios Apex...

Hi, I would like to simulate a NIOS system with modelsim but I have very strange results : it seems that the external SRAM (for the Nios Apex dev board) is incorectly adressed by the NIOS processor. I'm using quartus 2.2 and sopc builder 2.8 (NIOS 3.0) Here is what I'm doing : - the system is minimal (a 32 bit nios, an UART, an on chip memory, the external SRAM and two user interfaces). ...


Hex display with Quartus simulation

Started by Pratip Mukherjee in comp.arch.fpga18 years ago 1 reply

Hi, If I have a port defined as std_logic_vector(n downto 0), Quartus simulator is showing the individual bits in binary values. How do I make...

Hi, If I have a port defined as std_logic_vector(n downto 0), Quartus simulator is showing the individual bits in binary values. How do I make it display all the bits together in a hex mode. Thanks in advance. Pratip Mukherjee


Local nodes are not visible anymore after simulation (Altera Quartus II )

Started by Vazquez in comp.arch.fpga18 years ago 2 replies

Hello, I made a simulation by the means of a vwf-file. If I want to see the simulation results of signals which are neither inputs nor...

Hello, I made a simulation by the means of a vwf-file. If I want to see the simulation results of signals which are neither inputs nor output what do I have to do? Is there a difference between registered signals and combinatorical signals? Thanks a lot. Best regards A.Vazquez


Acek 1K - Quartus II - timing issues

Started by Kumaran in comp.arch.fpga18 years ago 6 replies

Hi all, I am targeting my design on Acex EP1K100QC208-3 FPGA. I did most of my development using Leonardo Spectrum synthesizer(2002) and Max +2....

Hi all, I am targeting my design on Acex EP1K100QC208-3 FPGA. I did most of my development using Leonardo Spectrum synthesizer(2002) and Max +2. My license for leonardo expired, and I decided to use Quartus II(v3.0). When I compile using Quartus, Iam getting a negative slack time for one of my clock. when I compiled the same FPGA code using LS and Max +2, I did not have any timing issues . I...


State Machines....

Started by stan in comp.arch.fpga18 years ago 27 replies

hi ... I have a question for the experts , I am doing a post mortem of my last project , it was a communication processor that was basicly a lot...

hi ... I have a question for the experts , I am doing a post mortem of my last project , it was a communication processor that was basicly a lot of dataflow paths controlled by several rather complex state machines ( 100-200 states ) , I did the design by thinking out the control and drawing the state diagrams and then coding them into VHDL for Quartus and into a Stratix .. it worked , after...