Quartus II Node Finder

Started by Vazquez in comp.arch.fpga18 years ago 1 reply

Dear Sir or Madame, attached you see a test project file. After compiling the design I open the Node Finder. I use the following filter :...

Dear Sir or Madame, attached you see a test project file. After compiling the design I open the Node Finder. I use the following filter : Design entry (all names) Why is the signal "vector_out" (entity test.vhd) (which is concurrently assigned by the registered signal "l_vector") and the corresponding port map signal (toplevel entity) "l_vector_out" shown to be combinatorial althou...


How to set 'set up time' in a Quartus Tool for a PCI Device

Started by naveen in comp.arch.fpga18 years ago 2 replies

Hi all, I have a small clarification. I am using Quartus 2 Tool for Synthesis and Place and route of a PCI System. I want to know if...

Hi all, I have a small clarification. I am using Quartus 2 Tool for Synthesis and Place and route of a PCI System. I want to know if we can set some options for set up time for PCI Clock Seperately. Thanks Naveen


memory

Started by bhb in comp.arch.fpga18 years ago

Hi, I'm looking for a VHDL example code to implement a DDR memory in a Altera 'Stratix'. (not a controler), with use of RAS, CAS,...

Hi, I'm looking for a VHDL example code to implement a DDR memory in a Altera 'Stratix'. (not a controler), with use of RAS, CAS, etc... There is many example of memory in Megawizard of Quartus (DP-RAM, FIFO), but I can't find DDR. I would like to have this DDR include in specific memory block (M-RAM or M512 or others). Thanks for your help, bhb


Quartus generics and vhdl

Started by JohhnyNorthener in comp.arch.fpga18 years ago 2 replies

P L E A S E somebody help. I have a design of mixed .gdf and .vhd files that were created in MaxPlusII, which I have imported it into Quartus...

P L E A S E somebody help. I have a design of mixed .gdf and .vhd files that were created in MaxPlusII, which I have imported it into Quartus II v3.0 SP2. What I am trying to do is to convert the complete design into VHDL ONLY The reason for doing this is so that i can do a functional simulation of my design prior to synthesising it - synthesis currently takes 4 hours ! ! The prob...


Hold violation and PLL

Started by a2zasics in comp.arch.fpga18 years ago 2 replies

Hi, I have a problem on quartus II 3.0 software. I am using enhanced PLL and a set of input registers with FAST INPUT REG = on constraint....

Hi, I have a problem on quartus II 3.0 software. I am using enhanced PLL and a set of input registers with FAST INPUT REG = on constraint. Thus i get about 1 ns delay of pad to IOB flop on datapath. However delay of clock from PLL to IOB flops is higher around 3 ns. Thus i get a hold violation of 2 ns. Anyone has any suggestions as to how i can eliminate this hold violation. Shardendu


How to assign inferred logic to resource in Quartus

Started by cruzin in comp.arch.fpga18 years ago 2 replies

Hi, I have a chain of registers to delay a certain wide signal 5 clocks. Quartus infers altshifttaps from this, which is fine because it...

Hi, I have a chain of registers to delay a certain wide signal 5 clocks. Quartus infers altshifttaps from this, which is fine because it saves me LEs. Unfortunately the M512 where it places the inferred shift register causes a long delay to and from the rest of logic. I want to manually assign this inferred shift register to a specific M512 for timing purposes. My question is two-fol...


Quartus-II question

Started by Pratip Mukherjee in comp.arch.fpga18 years ago 4 replies

Hi, I am trying to use AVRCore project from opencores.com on ACEX1K100-3 FPGA. Timing summary tells me that maximum clock is 11.xxx MHz. Since...

Hi, I am trying to use AVRCore project from opencores.com on ACEX1K100-3 FPGA. Timing summary tells me that maximum clock is 11.xxx MHz. Since my external clock is 40MHz, I inserted a divide by 4 counter before feeding it to the CPU clock. But Quartus still says that max. clock is 11.xxx MHz. How's that, shouldn't it be now 44.xxx MHz, assuming the input counter can count to 44MHz. I am...


FPGA CAD researchers: documentation, APIs, file formats & tutorials for academics to interface to Quartus

Started by Vaughn Betz in comp.arch.fpga18 years ago 1 reply

I am pleased to announce that Altera has opened up its Quartus II CAD suite to university researchers. The Quartus University...

I am pleased to announce that Altera has opened up its Quartus II CAD suite to university researchers. The Quartus University Interface Program, or QUIP, toolkit is designed to enable university (or other) researchers to plug new CAD tools and ideas into the Altera Quartus II CAD flow. QUIP describes Altera's devices, interfaces by which data can be sent into the Quartus II software at va...


Tutorials for ISE and Quartus

Started by Jean Nicolle in comp.arch.fpga18 years ago 1 reply

I've posted 2 (very graphical) tutorial for ISE and Quartus. ISE: http://www.fpga4fun.com/ISEQuickStart.html Quartus:...

I've posted 2 (very graphical) tutorial for ISE and Quartus. ISE: http://www.fpga4fun.com/ISEQuickStart.html Quartus: http://www.fpga4fun.com/QuartusQuickStart.html These are very simple - covers only device selection, pin assignment, and how to get the bit file. Still if you never saw the particular software in action, that might be the occasion. Have fun! Jean


Verilog Benchmarks for FPGA research

Started by news in comp.arch.fpga18 years ago

As it is my first time to comp.arch.fpga I will briefly mention that I'm working on a front-end verilog compiler that targets both academic...

As it is my first time to comp.arch.fpga I will briefly mention that I'm working on a front-end verilog compiler that targets both academic FPGAs as well as Altera's Quartus Flow. I am at a point where I need benchmarks. I have searched the web as well as www.opencores.org, but I need more. The main aspect of the benchmark which would be most useful is both size (actual transistor ...


after the synthesis total logic elements are equal zero

Started by Andre in comp.arch.fpga18 years ago 1 reply

Hi! I'm trying to synthecize a pic VHDL core on Altera Quartus II web edition, but when I make changes on the ROM.vhdl(It's using...

Hi! I'm trying to synthecize a pic VHDL core on Altera Quartus II web edition, but when I make changes on the ROM.vhdl(It's using Case-When clauses), the compiler reports: ; Total logic elements ; 0 ; ; Total pins ; 20 ; ; Total memory bits ; 0 ; ; Total PLLs ...


Timing Simulation ModelSim / Quartus

Started by Cornel Arnet in comp.arch.fpga18 years ago 2 replies

Hi there, I want to perform a timing simulation with ModelSim SE5.7e from the output generated by Quartus II 3.0. So, I add "mydesign.vho" to...

Hi there, I want to perform a timing simulation with ModelSim SE5.7e from the output generated by Quartus II 3.0. So, I add "mydesign.vho" to my modelsim project and it compiles without any errors or warnings. However, when I try to load the design for simulation (without *.sdo for now) the following is printed out: # Compile of mydesign.vho was successful. vsim work.mydesign(structure...


QUIP( Altera ) interseting But ?????

Started by Hayder Mrabet in comp.arch.fpga18 years ago

Hi everyone, 1. Where can i find a free Version of Quartus on Linux OS. I would like to test it. 2. is there any chance to apply QUIP's...

Hi everyone, 1. Where can i find a free Version of Quartus on Linux OS. I would like to test it. 2. is there any chance to apply QUIP's softwares on architectures that are other than Altera's devices.( Academic tools SIS+VPR allow this) Thanks in advance -- Hayder.Mrabet UPMC LIP6/ASIM Tel: 01 44 27 71 23


QUIP ( advance)

Started by Hayder Mrabet in comp.arch.fpga18 years ago 1 reply

Hi everyone, 1. Where can i find a free Version of Quartus on Linux OS. I would like to test it. 2. is there any chance to apply QUIP's...

Hi everyone, 1. Where can i find a free Version of Quartus on Linux OS. I would like to test it. 2. is there any chance to apply QUIP's softwares on architectures that are other than Altera's devices.( Academic tools SIS+VPR allow this) Thanks in advance --


Non deterministic routing in Quartus 3.0 ?

Started by g. giachella in comp.arch.fpga18 years ago 6 replies

I have launched the place & route of the same project on two different machines, a PC 2.6 GHz (WIN 2000) and a COMPAQ XEON 700 MHz Workstation...

I have launched the place & route of the same project on two different machines, a PC 2.6 GHz (WIN 2000) and a COMPAQ XEON 700 MHz Workstation (WIN NT 4). Same project means same .vhd, .edf, .csf, .psf, .ssf, .esf, .quartus files. The QUARTUS release is the same (same build, same SP). I obtained two different placements and two different compile times (PC = 1h 40 min, Workstation = 5h 22 min...


error in Quartus

Started by chris in comp.arch.fpga18 years ago 3 replies

First of all i would like you to apologize if what i am going to ask has been answered before.Although i searched until now i didn't find...

First of all i would like you to apologize if what i am going to ask has been answered before.Although i searched until now i didn't find anything helpful. My problem is that when i try to compile a package in Quartus which has only components i receive the error : node instance instantiates undefined entity float_pkg. The same file has been compiled successfully in Modelsim withous changing...


Quartus doesn't work with Pentium Hypertheading!

Started by SDL in comp.arch.fpga18 years ago 2 replies

Hi, I have compiled with Quartus II 3.0 SP2s a project that fills a Cyclone C12 for 89%. Quartus ends the work later around 2.30 hours...

Hi, I have compiled with Quartus II 3.0 SP2s a project that fills a Cyclone C12 for 89%. Quartus ends the work later around 2.30 hours (Pentium 4 - 2.8Ghz). If I try to compile the same project on a PC with processor Intel Pentium 4 with Hypertheading technology, Quartus doesn't succeed in ending the fitting, after 24 hours it is I still stop to the 80%. In the same PC I succeed in quickl...


Wer kennt sich mit Quartus von Altera aus?

Started by Anton in comp.arch.fpga18 years ago 6 replies

Hallo Ich bin Anf?nger und m?chte einen CPLD von Altera programmieren und sp?ter einen FPGA. Leider kann ich nicht allzugut english. Deshalb...

Hallo Ich bin Anf?nger und m?chte einen CPLD von Altera programmieren und sp?ter einen FPGA. Leider kann ich nicht allzugut english. Deshalb such ich jemand der sich gut damit auskennt und ich ihm eine Datei zur begutachtung schicken kann. Ich w?re sehr froh. Ich verwende das Programm Quartus 2 und mache dies mit "Schmatic" und nicht mit VHDL da ich noch zuwenig Erfahrung habe. Mi...


Differences between Xilinx ISE and Altera Quartus software

Started by Jean Nicolle in comp.arch.fpga18 years ago 21 replies

Hi all, I tried to summarize the differences in a table. http://www.fpga4fun.com/table.html Sorry about the link, it wasn't easy to...

Hi all, I tried to summarize the differences in a table. http://www.fpga4fun.com/table.html Sorry about the link, it wasn't easy to duplicate the table in text form for this posting. Things I'd be interesting to hear about: 1. is the info accurate? 2. did I miss important features that differentiate the 2 software? (without getting into details, these are big software...) The tabl...


Quartus II and Synthesis

Started by JohhnyNorthener in comp.arch.fpga18 years ago 3 replies

Any advice please. I am creating a parallel uP interface to my fpga and i have separate 'processes' for the read and write functions. My...

Any advice please. I am creating a parallel uP interface to my fpga and i have separate 'processes' for the read and write functions. My question is : Will quartus synthesise separate address decoders - one for the read and one for the write, or is it 'clever' enough to munge the two together in the same decoder when synthesising ? (not sure of the tech term but is this resource sharing ?...