Quartus II taking forever to compile

Started by ted in comp.arch.fpga18 years ago 10 replies

I am compiling a design for the Acex EP1k50 using Quartus II version 3. The FPGA device is about 20% full, but I am finding compilation times...

I am compiling a design for the Acex EP1k50 using Quartus II version 3. The FPGA device is about 20% full, but I am finding compilation times are taking longer and longer (Currently 14 minutes) They also seem to be increasing disproportionatley to the amount of extra functions added. For example, compilation was taking 7-8 minutes last week. Since then I have only added very few functions, ...


[Quartus] File folders changed -> errors

Started by Anonymous in comp.arch.fpga18 years ago 2 replies

Hi there, I use Quartus II v3.0 to work on my Altera designs and I have a problem. Recently I reorganized my hardrive and moved some folder...

Hi there, I use Quartus II v3.0 to work on my Altera designs and I have a problem. Recently I reorganized my hardrive and moved some folder locations... My old projects open fine from new locations and all components are found correctly when I double-click in the schematics window. When I try to locate the component in the messages window (by double clicking on the error line) the program ...


[Altera/Quartus] Tools to regenerate block schematics from .vhd files

Started by Anonymous in comp.arch.fpga18 years ago 4 replies

I am kind of new to FPGA design and I have to understand a circuit given as a set of hierarchical .vhd files (top level and two-three lower...

I am kind of new to FPGA design and I have to understand a circuit given as a set of hierarchical .vhd files (top level and two-three lower levels), but it would be kind of nice to see it layed out on a piece of paper... Is there a tool to generate schematics from vhd files to visualize vhd?


Can Altera NIOS be synthesized on non-cyclone/stratix FPGAs?

Started by Ben Nguyen in comp.arch.fpga18 years ago 1 reply

We have Quartus III at school, but only have the Altera UP2 development board to work with. It only has 70k gates, so Im guessing it wont be...

We have Quartus III at school, but only have the Altera UP2 development board to work with. It only has 70k gates, so Im guessing it wont be enough. Also does anyone know of a low cost (


Manual Partitioning to Multiple FPGAs

Started by tushit in comp.arch.fpga18 years ago 6 replies

Hi, I have a design which does not fit on my Altera Stratix device. I need to split it onto 2 Stratix devices. Is it possible to manually...

Hi, I have a design which does not fit on my Altera Stratix device. I need to split it onto 2 Stratix devices. Is it possible to manually do this? I can't afford a partitioning software. The clock frequency for the design after fitting will be around 30MHz and I can run the design at a speed slower than that achieved after fitting. So can I safely operate the design at say 20Mhz if Quartus ...


FPGA info from Embedded World 2004/Nuerrnberg

Started by Antti Lukats in comp.arch.fpga18 years ago

Embedded World 2004. Nuernberg, Review: First impression, FPGA vendors had very little presence there. Altera Xilinx, Triscend, Lattice where...

Embedded World 2004. Nuernberg, Review: First impression, FPGA vendors had very little presence there. Altera Xilinx, Triscend, Lattice where there, but in really small booths. Altera: the Quartus Suite CD was available for immediate pick-up, this CD should containt all the tools to work with NIOS evaluation version (Altera webdownloads do not include NIOS eval ASFAIK at the moment). Quar...


spying on signals in Quartus (newbie question)

Started by Vadim Rusu in comp.arch.fpga18 years ago 1 reply

Hi, When debugging a design one can assign inside the VHDL code debug pins. However, if after compiling and everything I decide to look for...

Hi, When debugging a design one can assign inside the VHDL code debug pins. However, if after compiling and everything I decide to look for some other signal of choice (that are not pins), in the simulation, QUARTUS will give me a list of uninteligible names. Is there any way around this? Signal Tap seems to work only with a physical FPGA via JTAG. Thanks Vadim


VHDL: Use of literal '1' on an input port ?

Started by Rajeev in comp.arch.fpga17 years ago 6 replies

Hello all, I'm still working with DSPBuilder. Here's a VHDL problem that I can fix but don't understand. DSPBuilder.vhd has a...

Hello all, I'm still working with DSPBuilder. Here's a VHDL problem that I can fix but don't understand. DSPBuilder.vhd has a line obj:lpm_add_sub port map (cin => '1'); Quartus is happy with this, and in fact I use constant port values in my own VHDL all the time. But Model Technology (Altera Edition 5.7e) complains: # ** Error: Actual for formal cin is not a signal.


Fan Out Problem..

Started by SneakerNet in comp.arch.fpga17 years ago

Hello FPGA gurus.. I am designing a micro using Quartus II v4.0 and the target FPGA is Flex10K (EPF10K20RC240-4). I know it's a very outdated...

Hello FPGA gurus.. I am designing a micro using Quartus II v4.0 and the target FPGA is Flex10K (EPF10K20RC240-4). I know it's a very outdated FPGA, but that's all I have :( The ALU unit when I compile stand along compiles and works as expected. However when the ALU is combined with the rest of the micro, during 'analysis & synthesis' I get a long list of warning.. .. here is the warning ...


Quartus for linux

Started by lbroto in comp.arch.fpga17 years ago 3 replies

Hi ! I'm lookink for a quartus web edition for Linux. I read some news but I don't manage to find if a such version exist. If it exists,...

Hi ! I'm lookink for a quartus web edition for Linux. I read some news but I don't manage to find if a such version exist. If it exists, where can I download it ? ( on altera website, I see quartus 4 bus this version doesn't work under linux). Thank's a lot, -- Laurent


Problems with Quartus 2 v4 under Linux

Started by in comp.arch.fpga17 years ago 2 replies

Hello, I have installed the latest Quartus version for Linux, applied the service pack 1 and still have problem with it: as soon as I want to...

Hello, I have installed the latest Quartus version for Linux, applied the service pack 1 and still have problem with it: as soon as I want to edit my VHDL top design file, Quartus crashes with no error message. I have removed all the accentuated letters but it did not resolved the problem. I am running a RedHat 9, I know it is not officialy supported but Altera did modify the scripts to i...


Altera Quartus Web Edition license...

Started by Kelv...@ SG in comp.arch.fpga17 years ago

I was used to Xilinx ISE already now I want to learn Quartus for some work experience... I like the GUI but I don't understand why must Altera...

I was used to Xilinx ISE already now I want to learn Quartus for some work experience... I like the GUI but I don't understand why must Altera deliver the Chip Editor but not license it!!! And why they can't give a permanent license... Kelvin


how to pass a date user code from Synplify to Quartus?

Started by Pierre-Louis in comp.arch.fpga17 years ago 1 reply

Hello, At this time I write manually in the field "user code" of Quartus an hexadecimal 8 digits timebased code, which is displayed in the...

Hello, At this time I write manually in the field "user code" of Quartus an hexadecimal 8 digits timebased code, which is displayed in the window of the FPGA programmer. And often, I forget to to fill up this field in the setting of Quartus, and I read back FFFFFFFF! I have a lot of different FPGA to synthetise , so I start up Symplify in a loop in a TCL script, and then Quartus is launc...


generic mapping

Started by Steve Wenner in comp.arch.fpga17 years ago

Hello, I am trying to create a test file to get a handle on 1. generic mapping and 2. multiple architectures within a file. Could someone tell...

Hello, I am trying to create a test file to get a handle on 1. generic mapping and 2. multiple architectures within a file. Could someone tell me what I am doing wrong? I am using the latest Quartus freeware however it doesn't seem to like how I have called the architecture from the top level file (tester). thanks much, -- Steve Wenner begin 666 tester.vhd M;&EB 2!)145%.P


NIOS: Run program from SDRAM

Started by Maciej Witaszek in comp.arch.fpga17 years ago 5 replies

Hi, I have the NIOS developer board with APEX FPGA.It has a SODIMM socket for SDRAM module. I use a Micron MT8LSDT864HG-10ECS. I make a Quartus...

Hi, I have the NIOS developer board with APEX FPGA.It has a SODIMM socket for SDRAM module. I use a Micron MT8LSDT864HG-10ECS. I make a Quartus project based on verilog/standard_32. I use nios_32 CPU. I create a new memory configuration based on Micron datasheet and I put it into class.ptf from altera_avalon_new_sdram_controller. I write a simple program that can read and write memory maped...


Trouble with Altera DSP Builder Licensing while trying to use Signal Compiler...

Started by Jon Parker in comp.arch.fpga17 years ago 2 replies

I have a DSP development kit, Stratix Edition. I obtained a license for the development kit, using the...

I have a DSP development kit, Stratix Edition. I obtained a license for the development kit, using the link: https://mysupport.altera.com/lic/devKitNic.asp?product=stratix I received the license, installed it per the instructions. Quartus II seems to work OK but when I try to run the Filtering Reference Design Lab, exercise 3, and run the Signal Compiler 2.1.3, I get the error message ...


Slack gets worst as I relax timing

Started by tushit in comp.arch.fpga17 years ago 2 replies

Hi, I am using QuartusII 3.0. I setup a tsu requirement on some input pins and quartus did a P&R and said it could not meet the tsu by 0.5ns...

Hi, I am using QuartusII 3.0. I setup a tsu requirement on some input pins and quartus did a P&R and said it could not meet the tsu by 0.5ns on only one of the paths. So I relaxed my tsu by about 1ns on all pins and did an incremental fitting. Now Quartus came back and said it could not meet timing on about 15 paths by 1.5ns. Why is this? Is there anyway of adding more predictibility in the ...


Design PAR in Stratix

Started by Peter Sommerfeld in comp.arch.fpga17 years ago 6 replies

Hi folks, I have a very simple design that uses 3 LEs in Stratix when compiled with either Quartus II 4.0 or Synplify. There must be something...

Hi folks, I have a very simple design that uses 3 LEs in Stratix when compiled with either Quartus II 4.0 or Synplify. There must be something I don't realize about the LE/routing architecture because I think it should/could use only 1 LE (see design below). I would think the design should connect the four terms to the 4 inputs of the LUT, feed this LUT's output to the D-input of the regis...


Error in SoPC Builder

Started by BJP in comp.arch.fpga17 years ago 3 replies

I'm using Quartus II 2.2 with service pack 2 and SoPC Builder 2.7 but when generating the system, I get a number of "grep: not found" errors. I...

I'm using Quartus II 2.2 with service pack 2 and SoPC Builder 2.7 but when generating the system, I get a number of "grep: not found" errors. I checked the Altera website but I couldn't find anything. Has anyone had similar problems/know why these errors are occuring? Please CC any replies to this group to me at pelletie@caltech.edu. Thanks! A more detailed report is as follows: Alter...


Quartus II Schematic Capture

Started by Gary Pace in comp.arch.fpga17 years ago 1 reply

Hi, Does anybody know how to turn off bounding box display in Quartus II schematic capture (if it's possible at all) ? Thanks, Gary.

Hi, Does anybody know how to turn off bounding box display in Quartus II schematic capture (if it's possible at all) ? Thanks, Gary.