Mutiple Quartus Instances?

Started by Kenneth Land in comp.arch.fpga17 years ago 4 replies

Anyone know if there are any gotcha's with working with multiple Quartus (II v. 4) projects on the same computer? I'd like to work several...

Anyone know if there are any gotcha's with working with multiple Quartus (II v. 4) projects on the same computer? I'd like to work several approaches simultaneously, but not if there are side effects - subtle or otherwise. Thanks, Ken


SignalProbe in Quartus...

Started by Kenneth Land in comp.arch.fpga17 years ago 2 replies

I'm trying to use SignalProbe to speed up the debugging process. I've got a number of testpoint pins that I've been assigning and...

I'm trying to use SignalProbe to speed up the debugging process. I've got a number of testpoint pins that I've been assigning and reassigning signals to in order to see the signals on an external logic analyzer. This works very well except the 10 min. compile just to change test signals is getting old. SignalProbe seems to be the solution to my problem but I'm not able to get it going co...


Logiclock TCL flow -- near completion

Started by Spyros Lyberis in comp.arch.fpga17 years ago 1 reply

Hi everyone, I'm near the completion of the final TCL flow for a Quartus II hierarchical design (based on a previous comp.arch.fpga...

Hi everyone, I'm near the completion of the final TCL flow for a Quartus II hierarchical design (based on a previous comp.arch.fpga discussion with the same subject). I ran into a problem while finalizing the TOP script, which is supposed to import the locked, back-annotated BOTTOM regions and simply connect them on a top level. The BOTTOM blocks, after they are fitted, are back-anno...


Anyone who has worked with Altera Cyclone???

Started by GreateWhite.DK in comp.arch.fpga17 years ago 3 replies

Hi I am struggleing with the bootcode. I have compressed the hardware image to half the size with the buildin tool. Now I want to compress the...

Hi I am struggleing with the bootcode. I have compressed the hardware image to half the size with the buildin tool. Now I want to compress the SW image. How can I do this? Can it be done from within Quartus II or must I do it in some other way? Hope u can help Thanks upfront GreateWhite.DK


EPCS4 Configuration+firmware, Quartus problem

Started by Jeroen in comp.arch.fpga17 years ago 2 replies

Hi, I'm using a Altera Cyclone 1C6 which contains a Nios. The FPGA is configured by an EPCS4. I want to store the firmware for the NIOS in the...

Hi, I'm using a Altera Cyclone 1C6 which contains a Nios. The FPGA is configured by an EPCS4. I want to store the firmware for the NIOS in the config device. This should be possible using ASMI. The problem is that I can't store the HEX file into the programming file for the configuration device. With Quartus, this should be done by converting the SOF file into a POF, and then insert the HE...


Quartus II Web Edition

Started by Florian Student in comp.arch.fpga17 years ago 4 replies

Dear Comp.Arch.Fpga I was just trying to get a license key for Quartus II Web Edition. It tells me that I need to provide a NIC to get the...

Dear Comp.Arch.Fpga I was just trying to get a license key for Quartus II Web Edition. It tells me that I need to provide a NIC to get the license key: * > Network Interface Card Number:*Your NIC number is a 12-digit hexadecimal number > that identifying the Windows workstation that serves the Quartus II Web Edition license. > You can find the NIC number for your network card by typing


Quartus Internal Errors

Started by tushit in comp.arch.fpga17 years ago 1 reply

Hi, I know I should be posting this to Altera Support, but I am in a bit of a hurry and hoping someone on the grp could advise me in...

Hi, I know I should be posting this to Altera Support, but I am in a bit of a hurry and hoping someone on the grp could advise me in parallel. I get a Quartus internal error while it's doing a P&R. Has anyone seen this before?? Any workarounds? I see this on 2 different machines both with enough RAM(1GB). ---------------------------------------------------------------------------- Interna...


Inversion of signals on synthesis

Started by ALuPin in comp.arch.fpga17 years ago 2 replies

Dear Sir or Madam, I have some phenomenon I do not know when synthesizing my VHDL description for my SRAM controller: The .vho-file from...

Dear Sir or Madam, I have some phenomenon I do not know when synthesizing my VHDL description for my SRAM controller: The .vho-file from Quartus is used for a timing simulation. When I have a look at internal signals of my controller like 'l_oe_bar', 'l_cs_bar','l_we_bar' I see in timing simulation with Modelsim that they are right inverted to my description, for example are they rese...


VHDL test bench in Quartus

Started by Pratip Mukherjee in comp.arch.fpga17 years ago 7 replies

Is it possible to write a test bench using VHDL in Quartus? When I tried I got an error message telling me that wait construct is not...

Is it possible to write a test bench using VHDL in Quartus? When I tried I got an error message telling me that wait construct is not supported. Is that true or am I making some mistake? Is there any way, may be using tcl, I can simulate a VHDL like test bench? Testbench using waveforms just does not work for me. Thanks. Pratip Mukherjee pratipm.remove_this@hotmail.com


Seven leading PC processors benchmarked on Quartus-II Web Ed place&route

Started by Michael S in comp.arch.fpga17 years ago 1 reply

Computer hardware enthusiast Johan De Gelas of aceshardware compared performance of seven top PC MPUs on Quartus-II Web Edition place and route...

Computer hardware enthusiast Johan De Gelas of aceshardware compared performance of seven top PC MPUs on Quartus-II Web Edition place and route task. Johan is a real professional when it comes to benchmarking computers. His results can be safely relied on. Probably the article would be of interest for participants of comp.arch.fpga http://www.aceshardware.com/read.jsp?id=65000307 Joh...


SOPC BUILDER - SOFTWARE GENERATION

Started by Julien Chevalier in comp.arch.fpga17 years ago 2 replies

Hello, Im' using Quartus 4 and SOPC Builder 4. I'm preparing a nios design, but i've got a trouble with software build. The point is that...

Hello, Im' using Quartus 4 and SOPC Builder 4. I'm preparing a nios design, but i've got a trouble with software build. The point is that the only way I have to generate the soft is to regenerate the whole system (both soft and hard). I obviously tried to use the command line tools, in vain. I tried to use the c macro offered in the generated modelsim do file ... but it's still not ...


Nios II really available ?

Started by geoffrey brown in comp.arch.fpga17 years ago 5 replies

Has anybody actually received updates to their Quartus and Nios toolkits to support Nios II ? Geoffrey

Has anybody actually received updates to their Quartus and Nios toolkits to support Nios II ? Geoffrey


can't trap custom ITon NIOS

Started by Julien Chevalier in comp.arch.fpga17 years ago 2 replies

Hello, I use quartus II 4.00 and SOPC builder 4.00 to build a NIOS system on a Stratix II board. I enabled the support for external...

Hello, I use quartus II 4.00 and SOPC builder 4.00 to build a NIOS system on a Stratix II board. I enabled the support for external interruptions, add a user defined IP connected via the provided avalon ahb bridge. Everything is ok. Then I try to use the interruption of the bridge, everything on the wire is ok until the data_master_irq gets high. The iq number is ok, NIOS makes a cou...


importing a design from maxplus2 to quartus II ver 3

Started by charles in comp.arch.fpga17 years ago 1 reply

I am trying to importing a design from maxplus2 to quartus, and having trouble for whole day. I imported the .acf file without too much...

I am trying to importing a design from maxplus2 to quartus, and having trouble for whole day. I imported the .acf file without too much trouble, and compiled it in quartus. Well, I got this weird error saying that LPM_DECODE's PIPELINE value has to be great 0 if clock is used. But PIPELINE parameter value does have a value of 1. So I don't know why it is doing that. So I updated the symb...


Quartus II - Disabling the Optimizer to use gate delay

Started by vadim in comp.arch.fpga17 years ago 3 replies

Does anybody know how can I disable the automatic optimizer in Quartus II to prevent it from eliminating redundant gates ? (I am trying to...

Does anybody know how can I disable the automatic optimizer in Quartus II to prevent it from eliminating redundant gates ? (I am trying to implement a delay line using a cascade of inverters, which Quartus removes during compilation since they are logically redundant.) thanks,


Altera Quartus II on Linux

Started by Miika Pekkarinen in comp.arch.fpga17 years ago 2 replies

Hello, I have Altera Quartus II 4.0 software and I managed to successfully install it on a Debian Linux machine (with Intel Pentium 4...

Hello, I have Altera Quartus II 4.0 software and I managed to successfully install it on a Debian Linux machine (with Intel Pentium 4 processor). However, always when I try to start the software, I will get the following messages: "Choose the preferred look and feel for the Quartus II software..." I select Quartus II and click OK. After that I will get: "MainWin licen...


Trying to remember how to use Quartus

Started by rickman in comp.arch.fpga17 years ago 6 replies

I would like to compile my new design to get a baseline number for resource usage. I have done this before, but I don't remember how to set up...

I would like to compile my new design to get a baseline number for resource usage. I have done this before, but I don't remember how to set up VHDL component libraries using Quartus. I have a common and a hardware library and a couple of VHDL source files for each. I can't find a way to associate the source files with the particular libraries. In Modelsim you just create the library and m...


Why does Quartus take 4 hours for a pin I/O change?

Started by David Rogoff in comp.arch.fpga17 years ago 2 replies

Sometimes the smart compile feature is great, but other times... I have a Stratix chip in Quartus II v4sp1. All I did was go into Assignment...

Sometimes the smart compile feature is great, but other times... I have a Stratix chip in Quartus II v4sp1. All I did was go into Assignment Editor and change a couple of pins from one I/O standard to another. There were no changes to my RTL code. As expected, it umped through synthesis in a minute. However, I expected the fitter to just take a few minutes since there was no placement o...


Forget the RAMs, I can't get Quartus to use the cascade chains!

Started by rickman in comp.arch.fpga17 years ago

I got my issues with the rams worked out and I belive I have an inferred design that will work in both Spartan 3 and ACEX chips with...

I got my issues with the rams worked out and I belive I have an inferred design that will work in both Spartan 3 and ACEX chips with few changes. I am trying to compile this design in Quartus II 3.0 and need for the software to use the cascade chain to provide fast bus muxes with lots of inputs. Right now my critical speed path (and one of the LE hogs) is a four input mux which I expect...


File format *.eqn in Altera IDE

Started by Markus Koechy in comp.arch.fpga17 years ago 2 replies

Hi, Altera Quartus-II produces *.eqn files. Does anyone know where I can find a detailed description of this fileformat? Thanks, Markus.

Hi, Altera Quartus-II produces *.eqn files. Does anyone know where I can find a detailed description of this fileformat? Thanks, Markus.