Quartus web editions vs licenced compatibility problems

Started by tns1 in comp.arch.fpga17 years ago 1 reply

I am using the QII4.0 SP1 web edition, SOPC4.0, Nios3.2 tools to develop on a Cyclone C4 system. I have had problems taking working projects...

I am using the QII4.0 SP1 web edition, SOPC4.0, Nios3.2 tools to develop on a Cyclone C4 system. I have had problems taking working projects created with the licensed versions of the tools, and re-building, re-generating, and compiling some C with the web edition, and getting the resulting pof & srec to work properly. If I leave the project alone and just re-compile the C, it works. Some...


nios-run ignores kbd.

Started by Nigel Gunton CEMS STAFF in comp.arch.fpga17 years ago 3 replies

Hi, I'm having problems getting nios-run -t to function correctly. The development platform is Quartus 3 sp2, SOPC 3.02 on Linux, Apex...

Hi, I'm having problems getting nios-run -t to function correctly. The development platform is Quartus 3 sp2, SOPC 3.02 on Linux, Apex board. I'm using the standard_32 example provided with the Nios kit 3.2. This builds (SDK and the hardware) without apparent problem, synthesises and can be downloaded via the jtag interface. executing nios-run -t results in the peripherals test menu bei...


seperate fpga programm and a table in altera

Started by roland voraberger in comp.arch.fpga17 years ago 1 reply

hello! i want to compile a design for a altera acex or cyclon and i want to put additionally a table into it (f.e. a .mif file) without...

hello! i want to compile a design for a altera acex or cyclon and i want to put additionally a table into it (f.e. a .mif file) without compiling it completely when changing the mif file (each delivered device has its own mif file or sth similar) what is the best way. does quartus have a possibility while burning to integrate the mif file into the pof file while burning? or should i use a...


Puzzled Simulating with 'X' input Quartus II v4.0 sp1

Started by Rajeev in comp.arch.fpga17 years ago 8 replies

I was simulating with some inputs set to 'X'=unknown on the inputs and observing defined outputs where I thought the output should be...

I was simulating with some inputs set to 'X'=unknown on the inputs and observing defined outputs where I thought the output should be indeterminate. Playing around some, I've reduced things to the following example. The outputs are as determined by QuartusII v4.0SP1. No optimizations turned on. The logic is not inside a process, but that doesn't make a difference. Quartus II v3.0 sp2 be...


Quartus II 4.0 SP1 Warning: Can't find design file .../projectname0.rtl.mif

Started by Manfred Balik in comp.arch.fpga17 years ago 1 reply

I allways get the Quartus Warning: Warning: Can't find design file .../projectname0.rtl.mif I found out, this file is from a large Constant...

I allways get the Quartus Warning: Warning: Can't find design file .../projectname0.rtl.mif I found out, this file is from a large Constant in my VHDL-Code which generates a ROM. The file is an "Other File" in the Project Navigator - if I "Remove this File from Project" the warning is generated at the next time compiling the project and the the file is in the list "Other Files" again. ...


Quartus SOPC Builder doesnt Recgnize my .elf file

Started by Rasquinha in comp.arch.fpga17 years ago

Hi, I am using Excalibuer FPGA with ARM 922T I need to download my Digital Design and My Embedded Code on to the chip for which the SOPC...

Hi, I am using Excalibuer FPGA with ARM 922T I need to download my Digital Design and My Embedded Code on to the chip for which the SOPC builder is not recgonizing my .elf generated by ECOS(RTOS). I have tried maniuplating the quartus makefile but no luck .I am abel to down load them independently ie my .elf or my hex file generated for my digital design but not both at the same time.If som...


Problem with LogicLock and register packing

Started by Peter Sommerfeld in comp.arch.fpga17 years ago 2 replies

Hi folks, I'm having a problem where I back-annotated the nodes of a LogicLock'ed SDRAM controller. The design was compiled with Auto Packed...

Hi folks, I'm having a problem where I back-annotated the nodes of a LogicLock'ed SDRAM controller. The design was compiled with Auto Packed Registers = MINIMIZE on Quartus 3.0 SP1. When I recompile the design, it fails, sometimes with as little as 2 nodes not being able to fit. This problem does not occur if I compile Reg Packing = NORMAL, so I assume register packing is causing problems....


Re: Altera FPGA's

Started by Leon Heller in comp.arch.fpga17 years ago 3 replies

"Ed" wrote in message news:cdjh0q$uvr$1@news8.svr.pol.co.uk... > Hi, > > Does anyone have any experience in programming Altera FPGA's? ...

"Ed" wrote in message news:cdjh0q$uvr$1@news8.svr.pol.co.uk... > Hi, > > Does anyone have any experience in programming Altera FPGA's? In particular > a FLEX8000. What development environment do you use and how much does it > cost? Do any free development environments exist for it (VHDL or Verilog)? > Also, is the programming hardware expensive? The free Quartus soft


Changing directory name in Quartus

Started by ALuPin in comp.arch.fpga17 years ago 3 replies

Hi, I have a directory called "TOP_PROJECT" in which I have several submodules. These submodules include VHDL files among each other. That...

Hi, I have a directory called "TOP_PROJECT" in which I have several submodules. These submodules include VHDL files among each other. That can be done in QuartusII --> Projekt --> Add/Remove Files in Project There you have to specify the path of the VHDL file you want to include. But what if I want to change the name of "TOP_PROJECT" directory to "TOP_PROJECT_X" ? Is that a problem?


Image export from Quartus?

Started by Andrew Holme in comp.arch.fpga17 years ago 3 replies

I'm designing a CPLD using the block diagram / schematic editor in Quartus II Version 4.1 Web Edition. Does anyone know a way to export the...

I'm designing a CPLD using the block diagram / schematic editor in Quartus II Version 4.1 Web Edition. Does anyone know a way to export the block diagram as an image? As far as I can see, the only way is to take a screen shots or else print to file.


Altera Bidi ports, Tristate Buffers & Prop. Delay?

Started by Pino in comp.arch.fpga17 years ago 6 replies

To all, I've discovered that there is some significant propagation delay between the input and bidirectional pin & bidirectional pin to...

To all, I've discovered that there is some significant propagation delay between the input and bidirectional pin & bidirectional pin to output pin in my simulation. I've compared the function LPM_BUSTRI within Quartus, a construction made up from Tri-state buffers within Quartus both within a BDF graph and also made my own configuration developed using VHDL. They all work similarily b...


Quartus warning

Started by Ted in comp.arch.fpga17 years ago 1 reply

I was trying to use the SDRAM controller without using the NIOS. I am now using the vhdl file generated from SOPC builder. Things are great...

I was trying to use the SDRAM controller without using the NIOS. I am now using the vhdl file generated from SOPC builder. Things are great during simulation i.e. However, when I try to synthesize it. I receive the following warning message: Warning: Can't pack node sdram_0:sdram_con_inst|m_addr[10] to I/O pin. +Warning: Can't pack logic cell sdram_0:sdram_con_inst|m_addr[10] and I/O no...


clock enable multicycle doesn't work with altera altshift_taps megafunction

Started by Wilhelm Klink in comp.arch.fpga17 years ago 1 reply

Has anyone encountered this problem with Altera/Quartus? I have a set of cascaded registers which can either be implemented using cascaded...

Has anyone encountered this problem with Altera/Quartus? I have a set of cascaded registers which can either be implemented using cascaded lpm_ffs or an altshift_taps unit. I have a main clock and an enable signal with a clock enable multicycle setting of 5. If I implement the registers using lpm_ffs then the required clock setup time is correctly stated in the timing analyzer as being 33...


Porting design constraints from A to X: help

Started by Nicolas Matringe in comp.arch.fpga17 years ago

Hello I am porting a PCI design from an Altera Stratix to a Xilinx Spartan3 and I am experiencing timing problems. I think the design is a bit...

Hello I am porting a PCI design from an Altera Stratix to a Xilinx Spartan3 and I am experiencing timing problems. I think the design is a bit underconstrained. Can somebody give me ISE equivalents for these Quartus constraints: FAST_INPUT_REGISTER FAST_OUTPUT_REGISTER TH_REQUIREMENT (probably something like IOBDELAY) DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS DECREASE_INPUT_DELAY_TO_OUTP...


Viewing internal nets during Quartus functional simulation

Started by Dalton Marris in comp.arch.fpga17 years ago 3 replies

I am trying to perform a functional simulation of a circuit which contains a multiplier (LPM_MULT) feeding into a ram cell (VHDL code). Using...

I am trying to perform a functional simulation of a circuit which contains a multiplier (LPM_MULT) feeding into a ram cell (VHDL code). Using the Node Finder, I have added the output of the multiplier "mult:inst|result" to my .vwf file, but I get the following warning message when I simulate: Warning: Can't find node mult:inst|result[0] for functional simulation. Ignored vector source fil...


Quartus, building "Safe" FMSs

Started by lecroy in comp.arch.fpga17 years ago 3 replies

I tried to contact Altera's upport on Safe FSMs and had to explain what can cause a FSM to get lost and about recovery. We even talked a bit...

I tried to contact Altera's upport on Safe FSMs and had to explain what can cause a FSM to get lost and about recovery. We even talked a bit about how some of the other tools like Synplicity handle this. This was Altera's responce: > Description: want to code a state machine and if it goes into an undefined > state, what does he need to code to reset the state machine > Unfotunately, i


How to make ByteBlaster II

Started by Antti Lukats in comp.arch.fpga17 years ago

The new serial devices can not be programmed with old Byteblaster, new ByteBlaster II is required. To make ByteBlaster II (or convert MV to...

The new serial devices can not be programmed with old Byteblaster, new ByteBlaster II is required. To make ByteBlaster II (or convert MV to II) only one change is needed: the loopback wire from pin 10 should go to pin 6 (not 7 as for MV), after this small mod Quartus programmer recognizes the cable as ByteBlaster II. The additional signal connections for Active serial programming can be found...


Quartus II v4.1 for PCs (-) Altera - new !

Started by te2 in comp.arch.fpga17 years ago

Quartus II v4.1 for PCs (-) Altera - new ! 18/Aug/2004 B02 Quartus II v4.1 for PCs (-) Altera for 16,000 more reasons, please send...

Quartus II v4.1 for PCs (-) Altera - new ! 18/Aug/2004 B02 Quartus II v4.1 for PCs (-) Altera for 16,000 more reasons, please send e-mail, astra35@freemail.gr, astra35@mail.gr, astra35@mailbox.gr,


Altera Quartus II 4.1 double-click on QPF-File doesn't work

Started by Manfred Balik in comp.arch.fpga17 years ago 3 replies

If I try to start my Quartus-Project by double-click on the QPF-File an error-window pops up. I found the mistake: in the path to start quartus...

If I try to start my Quartus-Project by double-click on the QPF-File an error-window pops up. I found the mistake: in the path to start quartus there are / instead of \ (I'm using Windows not Linux!). If I change the Link, the double-click will work one time, thereafter Quartus seems to changes the Link again to the wrong one :-( Can someone help? Thanks, Manfred


EPM7064LC44-7 - Not there in Quartus II...

Started by Drew in comp.arch.fpga17 years ago 2 replies

Hello guys, I am trying to Assign the Max Family EPLD - EPM7064 LC44-7 and run my compilation. But in the Assign Device I find EPM7064...

Hello guys, I am trying to Assign the Max Family EPLD - EPM7064 LC44-7 and run my compilation. But in the Assign Device I find EPM7064 SLC44-7. There are some significant differences between LC and SLC in terms of Max allowable freq, LCELL delay etc. Please let me know if anybody can find it in the Assign Device section. Thanks Drew