rocketio in serdes mode

Started by hanifkagdi in comp.arch.fpga11 years ago

Hi, Actually i am using rocketio wizard 7.1.I want to do conversion of 8 bit parallel data into serial stream using rocketio mgt for 3.125...

Hi, Actually i am using rocketio wizard 7.1.I want to do conversion of 8 bit parallel data into serial stream using rocketio mgt for 3.125 gbps. What frequency i have to apply on refclk,rxusrclk,rxusrclk2,txusrclk,txusrclk2?? I do not want to use crc and 8b10b module of rocketio mgt. Please suggest me any simple application for that.


Xilinx RocketIO problems

Started by John Stein in comp.arch.fpga10 years ago 6 replies

Hi. I am trying to establish a communication between two RocketIO driven Virtex2P FPGAs. I am currently simulating the design running into...

Hi. I am trying to establish a communication between two RocketIO driven Virtex2P FPGAs. I am currently simulating the design running into the following problem: When I set the RocketIO Transmitters (Xilinx GT_CUSTOM) into parallel loopback mode everything is fine (received data = sent data). Whenever I set it into serial loopback mode (or try to communicate with another RocketIO receiver) I...


Difference between virtex 4 rocketio MGT and viretex 5 rocketio GTP

Started by nagaraj in comp.arch.fpga10 years ago 5 replies

Hi, I m looking for differences between rocketio MGT and GTP (both architectural as well as the way they are used). please reply if anybody...

Hi, I m looking for differences between rocketio MGT and GTP (both architectural as well as the way they are used). please reply if anybody knows anything in this regard. Thanks, Nagaraj


SATA and RocketIO

Started by sg in comp.arch.fpga12 years ago 5 replies

Has anyone had any sucess in using RocketIO from Virtez 2 or Virtex 4 for Serial ATA applications? From the information collected on...

Has anyone had any sucess in using RocketIO from Virtez 2 or Virtex 4 for Serial ATA applications? From the information collected on various news groups and web sites, my understanding is SATA OOB cannot be done using RocketIO in Virtex 2s. Did any one try Virtex 4s? What is the comment from FPGA gurus out there? - sg


RocketIO over cable

Started by vt2001cpe in comp.arch.fpga11 years ago 10 replies

Anyone have experience with directly driving a cable with RocketIO? I am interested in any information/experiences/advice regarding linking two...

Anyone have experience with directly driving a cable with RocketIO? I am interested in any information/experiences/advice regarding linking two FPGAs via RocketIO over a cable. I have seen some signal characterization information for high-speed links over copper, but usually less than 800Mhz. I believe my implementation would use a a less than 1 meter, but would like to know it works at 3, 5,...


RocketIO success?

Started by Paul Smith in comp.arch.fpga13 years ago 12 replies

I'm considering the V2pro series for several projects. I've heard from someone with experience that there are problems with the RocketIO...

I'm considering the V2pro series for several projects. I've heard from someone with experience that there are problems with the RocketIO when a lot of other things are happening on the chip. This is thought to be a problem with the V2pro package. The evaluation boards only implement the RocketIO without a lot of other things going on in the part. Can anyone provide an example of ...


Virtex-4 RocketIO

Started by Peter Mendham in comp.arch.fpga11 years ago 2 replies

Dear all, I'm in the early stages of designing a board with a Virtex-4 FX on it which we are planning to use for development involving...

Dear all, I'm in the early stages of designing a board with a Virtex-4 FX on it which we are planning to use for development involving RocketIO. The other guys on the team have stated that it would be "really useful" to have the clock for the RocketIO fed from a programmable oscillator. We have a Virtex-II FX development board that has a similar arrangement, using a ICS8442 low jitt...


Rocketio, modelsim xe

Started by ndt in comp.arch.fpga11 years ago 2 replies

Hi, I'm trying to implement rocketio on xilinx fpga. Is there a way to simulate it using modelsim XE. I know for the PE, SE version its using...

Hi, I'm trying to implement rocketio on xilinx fpga. Is there a way to simulate it using modelsim XE. I know for the PE, SE version its using smartmodels or generating libraries. Also is there any basic programs using rocketio, architect (wizard can't simulate, core generator can't compile libraries for modelsim, and the program that came with the eval board uses multiple buses, memory ...


Changing SerDes speed on the V4FX RocketIO

Started by Josh Rosen in comp.arch.fpga11 years ago

Has anyone been able to dynamically change the SerDes speed on the V4FX RocketIO. I've been able to get the RocketIO to operate correctly at...

Has anyone been able to dynamically change the SerDes speed on the V4FX RocketIO. I've been able to get the RocketIO to operate correctly at both SDR rates (2.5GHz) and DDR (5GHz) rates using static parameters but when I try to change the speed dynamically the RocketIO enter a state where they never lock up at any speed. The only way to get them to operate again is to reload the bit stream. ...


Virtex-4 RocketIO and G.709 OTU-2

Started by in comp.arch.fpga11 years ago 14 replies

Hi all, Did some company already implemented G.709 OTU-2 on Virtex-4 using the RocketIO? In other words: the maximum bitrate of RocketIO is...

Hi all, Did some company already implemented G.709 OTU-2 on Virtex-4 using the RocketIO? In other words: the maximum bitrate of RocketIO is 10.3125 but OTU-2 is 10.709. Should Virtex-4 be definitively excluded or are there some tricks to achieve that challenge? Cheers Mehdi


Is there any version of Aurora protocol which works with LVDS instead of MGTs?

Started by Massoud in comp.arch.fpga10 years ago

Hi All, I reviewed LocalLink and Aurora protocol and it does not specifically say anything about RocketIO tranceivers. So I assumed that it...

Hi All, I reviewed LocalLink and Aurora protocol and it does not specifically say anything about RocketIO tranceivers. So I assumed that it could be implemented by using LVDS pins when higher speeds are not necessary. But its IP just works with RocketIO. - I am wondering if it's possible to implement it with diferrential pins other than RocketIO? - Does anybody know another pr...


Jitter calculation for RocketIO reference clock

Started by jean-francois hasson in comp.arch.fpga12 years ago

Hi, I am presently working on a design involving a RocketIO in a Virtex II Pro. I am looking at reference clocks for the PLL of the RocketIO...

Hi, I am presently working on a design involving a RocketIO in a Virtex II Pro. I am looking at reference clocks for the PLL of the RocketIO meeting among other things the jitter requirement related to the serial link frequency. I am wondering how to combine deterministic jitter and random jitter parameters of the oscillator. Is the total jitter the rms value of the two parameters or ...


Looking for a RocketIO expert in Ottawa, ON

Started by MM in comp.arch.fpga12 years ago

Just as the subject says I am looking for someone local who has experience in using RocketIO and possibly Aurora protocol for simple data...

Just as the subject says I am looking for someone local who has experience in using RocketIO and possibly Aurora protocol for simple data streaming. This is a contract position. Thanks, /Mikhail


Xilinx RocketIO receiver reset problem

Started by johnp in comp.arch.fpga11 years ago 2 replies

I'm connecting a V2Pro Rocket IO to a Agilent optical interface and am having problems getting the RocketIO receiver to reset properly and...

I'm connecting a V2Pro Rocket IO to a Agilent optical interface and am having problems getting the RocketIO receiver to reset properly and generate the correct data. The design originally used a Vitesse serial parallel interface chip and that worked fine. Since we have a spare RocketIO, we'd like to use it instead of the Vitesse chip. I'm running the link at 1062.5 Gbit/sec, so the refe


Xilinx GTP_DUAL: wizard or code ?

Started by tullio in comp.arch.fpga9 years ago 1 reply

I am using for the first time a Xilinx RocketIO module (I have years of FPGA experience though); normally I prefer to explicitly write on my...

I am using for the first time a Xilinx RocketIO module (I have years of FPGA experience though); normally I prefer to explicitly write on my code all the instatiations. Manual UG196 says:" The RocketIO GTP Transceiver Wizard is the preferred tool to generate a wrapper to instantiate a GTP_DUAL primitive." Any experience and advice about coding vs wizard in the case of RocketIO ? My app...


New to RocketIO

Started by Peter Mendham in comp.arch.fpga11 years ago

Dear all, I'm new to RocketIO and would appreciate any guidance from a hw design perspective. I am currently doing schematics for an...

Dear all, I'm new to RocketIO and would appreciate any guidance from a hw design perspective. I am currently doing schematics for an application specific development board and trying to work through the various demands from the datasheets and app notes, for example, the fact that it seems to need three additional LDO power supplies?!? Any hints and tips would be useful. TIA --...


RocketIO attribute for TLK301 or TLK2501

Started by John in comp.arch.fpga12 years ago

Anybody can advise me to configure the RocketIO attribute correctly to emulate TLK3101 or TLK2501 SerDes. John.

Anybody can advise me to configure the RocketIO attribute correctly to emulate TLK3101 or TLK2501 SerDes. John.


RocketIO attribute for TLK301 or TLK2501?

Started by John in comp.arch.fpga12 years ago

Anybody can advise me to configure the RocketIO attribute correctly to emulate TLK3101 or TLK2501 SerDes. John.

Anybody can advise me to configure the RocketIO attribute correctly to emulate TLK3101 or TLK2501 SerDes. John.


RocketIO, MGT documentation. Does MGT clcok have to be 50% duty cycle?

Started by Dale in comp.arch.fpga11 years ago 2 replies

Is it just me or is the documentation for the RocketIO (MGT) for the Xilinx Virtex4 very bad? I'm trying to find duty cycle requirements for...

Is it just me or is the documentation for the RocketIO (MGT) for the Xilinx Virtex4 very bad? I'm trying to find duty cycle requirements for the MGT clock. Is it OK to use a clock with a 40% duty cycle? Also, if anyone can point me to some better RocketIO (MGT) documentation for the hardware guys I'd appreciate it. I already have ug076. Thanks, Dale


Help on test RocketIO loopback

Started by Jin Cheng in comp.arch.fpga13 years ago

Hi, We have a VirtexPro40 on a PCI-Express board. Right now we want to write some rtl to test the RocketIO inside of the FPGA. Since I am new...

Hi, We have a VirtexPro40 on a PCI-Express board. Right now we want to write some rtl to test the RocketIO inside of the FPGA. Since I am new to this area, can anyone suggest some plan for testing. we have eight LED connected to the FPGA. Thanks. Jin