SDRAM controller.

Started by Anonymous in comp.arch.fpga15 years ago 3 replies

Hi Guys, I am writing a SDRAM controller (for the first time), its a Micron MT48LC16M16 sdram. I am having a little trouble coding it, i've...

Hi Guys, I am writing a SDRAM controller (for the first time), its a Micron MT48LC16M16 sdram. I am having a little trouble coding it, i've written some code for it but i am not sure if i am going along the right path or not ? Does neone has a little tutorial on how to code a sdram controller or perhaps a sdram controller that they wrote (doesnt matter for which SDRAM), nething that i coul...


For accessing my SDRAM,what should i do?

Started by ARRON in comp.arch.fpga15 years ago 8 replies

I try to access the SDRAM in my program, and wait for enough time before writing data to SDRAM,but i find the value of SDRAM is FF,what should i...

I try to access the SDRAM in my program, and wait for enough time before writing data to SDRAM,but i find the value of SDRAM is FF,what should i do ? what is wrong?


SDRAM Controller on a cyclone dev kit

Started by Nick in comp.arch.fpga16 years ago 2 replies

Hello, I've been unsuccessfully trying to use the SDRAM on my MJL Cyclone dev kit. I've tried the example (not very well documented) sold with...

Hello, I've been unsuccessfully trying to use the SDRAM on my MJL Cyclone dev kit. I've tried the example (not very well documented) sold with the dev kit, and tried the Altera IP Sdram controller. The way i do it : I connect the sdram controller to the sdram and use a small test module to check it reads and writes. I start with the initialisation sequence of the ram (nop for 100?s then...


ALTERA EPXA1 SDRAM BUG

Started by Ralf in comp.arch.fpga15 years ago

Hi all, have everyone experience about a second SDRAM with the Altera FPGA+HARCORE-CPU EPXA1? Its is unpossible for me to access the second...

Hi all, have everyone experience about a second SDRAM with the Altera FPGA+HARCORE-CPU EPXA1? Its is unpossible for me to access the second SDRAM. I used a modified "Hello World" program from ALTERA, Linux running on the hardcore CPU and ARMBOOT to address the second SDRAM (Chip-Select SD-CS1) device. But I always get the content of the first SDRAM (Chip-Select SD-CS0). Both SDRAM devices...


16-bit sdram and 32-bit opb bus

Started by Frank in comp.arch.fpga17 years ago 1 reply

Is it possible to use the opb sdram controller with a 32-bits opb bus to a microblaze one side and a 16-bits sdram to the other side? What if I...

Is it possible to use the opb sdram controller with a 32-bits opb bus to a microblaze one side and a 16-bits sdram to the other side? What if I do a 32-bits access to sdram. Will the controller convert this automatically in two 16-bits cycles? The datasheet of the opb sdram controller says: "Since the sdram will always be accessed to provide data the width of the OPB bus, ...". So it looks li...


WTD: WISHBONE SDRAM interface or some Vlog HDL synthesizing...

Started by Philip Pemberton in comp.arch.fpga10 years ago 4 replies

Hi guys, I'm (still) trying to chase down an issue with the SDRAM on an Enterpoint Drigmorn2 development board. Basically, the SDRAM is...

Hi guys, I'm (still) trying to chase down an issue with the SDRAM on an Enterpoint Drigmorn2 development board. Basically, the SDRAM is acting like the mythical Write Only Memory -- I can write stuff to it, but as soon as the address goes over 0x800, the readback is stuffed. Does anyone have either a known-working SDRAM IP core (ideally with a WISHBONE interface), or an SDRAM tester,...


SDRAM problem

Started by cool.rezaul in comp.arch.fpga11 years ago

Hi I am using Kingston 512MB SDRAM for my XUP virtex 2 pro development board. I am working on image filtering where I have to transfer the...

Hi I am using Kingston 512MB SDRAM for my XUP virtex 2 pro development board. I am working on image filtering where I have to transfer the image file to the SDRAM and then filter it by bring the data to the BRAM's. I am struck off into following steps: 1. How can I send a whole image file to the SDRAM. I can put some data on the SDRAM using the EDK C code which is as follows #define XPS_MEM_...


SDRAM Clock Skew

Started by Pouria in comp.arch.fpga15 years ago 4 replies

HI Everybody! I'm having a timing problem interfacing with my SDRAM bank. I'm using 256Mb MT48LC16M16 SDRAM from Micron, and want to operate...

HI Everybody! I'm having a timing problem interfacing with my SDRAM bank. I'm using 256Mb MT48LC16M16 SDRAM from Micron, and want to operate them at 100 Mhz. So far I have only been working at 40 Mhz. I'm using two DLLs (inside my VirtexII) one for clocking the FPGA and one for clocking the SDRAM. The design works if I DON'T use the external feedback from SDRAM_Clk to one of the DLL, but it...


DDR2 SDRAM and Virtex2Pro

Started by Sean Durkin in comp.arch.fpga16 years ago

Hi *, does anyone have any experience with DDR2 SDRAM-controllers in a Virtex2Pro? There's of course a bunch of ready-to-use controllers for...

Hi *, does anyone have any experience with DDR2 SDRAM-controllers in a Virtex2Pro? There's of course a bunch of ready-to-use controllers for DDR1 SDRAM, but for DDR2 it only says in Xilinx' "Memory Corner" that "The Virtex-II Pro built-in capabilities enable DDR2 SDRAM interfacing at data rates of 533 Mbps." But there's no examples, and in the usual xapps concerning DDR SDRAM DDR2 is n...


xilinx VP20 and SDRAM

Started by qudhs in comp.arch.fpga16 years ago

Hi! I have a XilinxVP20 chip with 2 PPC cores and a 32M SDRAM. what I want to do is to use the SDRAM as instruction memory for one of the...

Hi! I have a XilinxVP20 chip with 2 PPC cores and a 32M SDRAM. what I want to do is to use the SDRAM as instruction memory for one of the PPC cores, but I couldn't figure out how to upload the instruction data onto the SDRAM. thanks in advance! -yang


SDRAM in SPARTAN 3E

Started by Pablo in comp.arch.fpga14 years ago

Help!!!!!!!!! Hi, How can I write data into the ddr sdram with Microblaze and the OPB DDR. The SDRAM is 16MX16 and I have only found how can I...

Help!!!!!!!!! Hi, How can I write data into the ddr sdram with Microblaze and the OPB DDR. The SDRAM is 16MX16 and I have only found how can I test this memory. Can anyone tell me something about this????


SDRAM controller

Started by RANGA REDDY in comp.arch.fpga16 years ago 2 replies

Hi all, can anybody tell how autorefresh in SDRAM exactly works? suppose in SDRAM specifications it is mentioned that 64 ms, 4096...

Hi all, can anybody tell how autorefresh in SDRAM exactly works? suppose in SDRAM specifications it is mentioned that 64 ms, 4096 cycle refresh(15.6 us/row) what exactly it means and how we need to generate the autorefresh cycles. actually i am trying to upgrade the 512k*4*32 SDRAM(Fujitsu Make) to Micron Make 1M*4*32 SDRAM. FUJITSU specifies that 4K refresh cycles every 16ms, auto re...


SDRAM

Started by RANGA REDDY in comp.arch.fpga16 years ago 11 replies

Hi all, can anybody tell how autorefresh in SDRAM exactly works? suppose in SDRAM specifications it is mentioned that 64 ms, 4096...

Hi all, can anybody tell how autorefresh in SDRAM exactly works? suppose in SDRAM specifications it is mentioned that 64 ms, 4096 cycle refresh(15.6 us/row) what exactly it means and how we need to generate the autorefresh cycles. actually i am trying to upgrade the 512k*4*32 SDRAM(Fujitsu Make) to Micron Make 1M*4*32 SDRAM. FUJITSU specifies that 4K refresh cycles every 16ms, auto re...


Altera DDR SDRAM & external DSP

Started by Jerry in comp.arch.fpga16 years ago

The question is "Has anyone successfully integrated two DDR SDRAM controllers controlling one block of ram?" The alternate approach is to use...

The question is "Has anyone successfully integrated two DDR SDRAM controllers controlling one block of ram?" The alternate approach is to use the DSP HPI port as the transfer port between the shared SDRAM and the DSP. This would not rely on using the DSP DDR SDRAM controller to access the shared ram. The bandwidth takes a hit but the overall system preformance is not affected. Oh the inte...


xilinx spartan3e kit ddr sdram

Started by emu in comp.arch.fpga13 years ago 2 replies

Hi all, is there any open source DDR SDRAM controller IP available (VHDL) for the DDR SDRAM on this kit ?

Hi all, is there any open source DDR SDRAM controller IP available (VHDL) for the DDR SDRAM on this kit ?


DDR SDRAM controller for virtex 2 pro

Started by ralstef in comp.arch.fpga14 years ago

I want to use a DDR SDRAM on my virtex 2 pro platform; however the vhdl controller available is for a 256Mb micron SDRAM; mine is a kingston...

I want to use a DDR SDRAM on my virtex 2 pro platform; however the vhdl controller available is for a 256Mb micron SDRAM; mine is a kingston kvr266x64c25/512 with 512MBytes ( actually 64Mx64). Can anyone help me? is it possible to adapt the opencore controller for my SDRAM? how??


SDRAM controller

Started by FP in comp.arch.fpga12 years ago 4 replies

I am looking for a SDRAM controller for Xilinx Spartan3 device in Verilog. xapp 134 has one which targets virtex 2 devices. Xilinx MIG can be...

I am looking for a SDRAM controller for Xilinx Spartan3 device in Verilog. xapp 134 has one which targets virtex 2 devices. Xilinx MIG can be used for DDR and DDR2 SDRAMs. Can a DDR SDRAM controller be used to drive SDR SDRAM? What other options do I have?


store program in external sdram

Started by Tom in comp.arch.fpga17 years ago 1 reply

Hi, How do you store an entire program in external sdram, is it possible to declare all sections in the linker script to sdram (eventually...

Hi, How do you store an entire program in external sdram, is it possible to declare all sections in the linker script to sdram (eventually the boot section to bram) ? Or is there another way to get all data in the sdram ? thanks Tom


Yet another SDRAM design :)

Started by Anonymous in comp.arch.fpga16 years ago

Hello ALL, I am having hard time designing the schematic to interface conventional SDRAM chip to Virtex-4 FPGA. As a SDRAM we have selected...

Hello ALL, I am having hard time designing the schematic to interface conventional SDRAM chip to Virtex-4 FPGA. As a SDRAM we have selected Micron 256Mbit part with 32 bit wide data bus. Both packages a BGA, Virtex-4 is FF-672 type, SDRAM is FBGA-90. Our chips is planned to be located about 5-10mm (0.2-0.4 inches) from each other and the longest trace is suppose to be about 2.0-2.5 inches....


Why feedback clock in SDRAM controllers?

Started by valtih1978 in comp.arch.fpga9 years ago 11 replies

I see it in many SDRAM controllers, e.g. ftp://ftp.xilinx.com/pub/applications/xapp/xapp608.pdf, and nobody explains WHY The extranal...

I see it in many SDRAM controllers, e.g. ftp://ftp.xilinx.com/pub/applications/xapp/xapp608.pdf, and nobody explains WHY The extranal feedback trace must equal to CK len. Ok. This means that SDRAM will be clocked in phase with the FPGA system. How does it ensure that cmd/addr arrives to SDRAM in proper time, half cycle earlier of CK? In the more recommended xapp266 and xapp253, the e...