NIOS II - Instantiating array on SDRAM

Started by zg in comp.arch.fpga17 years ago 1 reply

Hi group, I am trying to develop a digital camera around the NIOS II using the Stratix development board. I need to instantiate a large...

Hi group, I am trying to develop a digital camera around the NIOS II using the Stratix development board. I need to instantiate a large buffer (2MW) in the SDRAM. In my code I instantiated my array like this: alt_u16 Image_Buffer[0x2000000] __attribute__ ((section (".sdram")); The SOPC builder has an SDRAM of 4MX32bits, so I should have enough space to instantiae the array. When I am...


how can i save my received data into the SDRAM?

Started by ARRON in comp.arch.fpga16 years ago 5 replies

I have receive large character data from RS232, i want to save it in the SDRAM memory, i find the SDRAM is 8M*32, but the character is 8bits,not...

I have receive large character data from RS232, i want to save it in the SDRAM memory, i find the SDRAM is 8M*32, but the character is 8bits,not 32bits, if i write a character into an Unit of SDRAM, next 24bits memory is wasted, and i find some data is not correct, how can i use the SDRAM correctly and efficiently?


One or two DLLs for a SDRAM controller?

Started by Marius Vollmer in comp.arch.fpga16 years ago 5 replies

Hi, I have a Xess board with a Xilinx Spartan 3 (XC3S1000) on it and a SDRAM. There is of course code out there for accessing this...

Hi, I have a Xess board with a Xilinx Spartan 3 (XC3S1000) on it and a SDRAM. There is of course code out there for accessing this SDRAM from the FPGA, but I decided to write my own controller, just so that I could learn what is going on. Now, all the SDRAM controllers that I have looked at use two DLLs (or DCMs) to produce the main clock for the controller. The Xilinx Applicatin note...


DDR SDRAM demo for Spartan-3E starter kit?

Started by Anonymous in comp.arch.fpga13 years ago 11 replies

I have a Xilinx/Digilent Spartan-3E starter kit Rev D (with 46V32M16 -6T F). Is there any *simple* demo that stores a picture bitmap in the...

I have a Xilinx/Digilent Spartan-3E starter kit Rev D (with 46V32M16 -6T F). Is there any *simple* demo that stores a picture bitmap in the builtin DDR SDRAM and sends the bitmap to the VGA port continously ..? Is it correct that the DDR SDRAM won't go below 75 MHz due the DLL used ..? (Micron indicate that SDRAM can go as low as a few kHz in clock frequency if needed) I had a look at ...


DDR SDRAM Controller

Started by ada in comp.arch.fpga15 years ago 30 replies

Hi there, unfortunately I have problems with DDR SDRAM Controller. I have an Avnet board with Xilinx Virtex-II FPGA (xc2v4000-ff1152)and Micron...

Hi there, unfortunately I have problems with DDR SDRAM Controller. I have an Avnet board with Xilinx Virtex-II FPGA (xc2v4000-ff1152)and Micron DDR SDRAM DIMM (MT4VDDT1664HG). I am using opencores DDR SDRAM controller. I have already adapted it and simulation with ModelSim works fine but I have real problems with the board. I synthesize and implement my design with Xilix Project Navigator 7.1 a...


why my SDRAM test failed in EDK7.1i?

Started by ARRON in comp.arch.fpga16 years ago

I have built a new project with two SDRAM(each 32M) in EDK7.1i,and used the original memory test program,i find the first SDRAM test is...

I have built a new project with two SDRAM(each 32M) in EDK7.1i,and used the original memory test program,i find the first SDRAM test is successful,BUT the second SDRAM test has failed,Why?What is wrong with it? Any advice is appreciated!!!


Help getting sdram running with EDK.

Started by john...@gmail.com in comp.arch.fpga14 years ago 4 replies

I've been struggling for weeks to get sdram to work correctly on a newly designed board. I was hoping that someone might have some suggestions...

I've been struggling for weeks to get sdram to work correctly on a newly designed board. I was hoping that someone might have some suggestions to help me out with my struggle here. This is what I am seeing: I am using EDK 8.1 to build a Microblaze system with a sdram controller. The memory is a micron 48LC16M8A2tc-75 part. I have verified that writes look correct using chipscope. I've ...


SDRAM Controller timing problem

Started by etrac in comp.arch.fpga17 years ago 10 replies

Hello, I have implemented my own SDRAM controller in a Virtex II component in order to use SDRAM modules Sodimm-PC133 (133 MHz...

Hello, I have implemented my own SDRAM controller in a Virtex II component in order to use SDRAM modules Sodimm-PC133 (133 MHz frequency). My problem is that this block seems to work very well with MICRON Sdram modules, but it is not fully stable with SMART modules. It seems to be the burst reading which causes some bit errors (not many, we have at worst 25 bit errors on 32Mb files). ...


Debugging SDRAM interfaces

Started by Philip Pemberton in comp.arch.fpga11 years ago 15 replies

Hi guys, I could really use some help from an SDRAM / FPGA guru here... I've got an SDRAM controller IP core -- specifically, the sdram_wb...

Hi guys, I could really use some help from an SDRAM / FPGA guru here... I've got an SDRAM controller IP core -- specifically, the sdram_wb core by Stephen Williams, available from the Git repository . This core works fine on the Altera DE1, with a 16-bit-wide 64Mbit (1M*16*4bank) PowerChip SDRAM, P/N A2V64S40CTP. The FPGA is a Cyclone II 2C20


Spartan3 interface with DDR SDRAM

Started by FP in comp.arch.fpga13 years ago 2 replies

I would like some suggestions on interfacing the Xilinx Spartan3 device with a DDR SDRAM. The idea is to build a controller that will set up the...

I would like some suggestions on interfacing the Xilinx Spartan3 device with a DDR SDRAM. The idea is to build a controller that will set up the DDR-SDRAM so that I can do a burst read of a page of data into a block of internal SRAM (dual port). Your help is appreciated


DDR SDRAM

Started by ALuPin in comp.arch.fpga17 years ago 6 replies

Hi, I have a question concerning the write operation for a DDR SDRAM with a burst length of 1: If you have a look at...

Hi, I have a question concerning the write operation for a DDR SDRAM with a burst length of 1: If you have a look at http://mitglied.lycos.de/vazquez78 you can see the sequence of eight back-to-back write requests that go to two different rows in the DDR SDRAM device. In the shown instance (DDR SDRAM Controller MegaCore User Guide Altera) the burst length is one on the Controller Lo...


Using SDRAM on Xilinx AFX V2P board

Started by Michael Dales in comp.arch.fpga17 years ago 5 replies

Hi there, We have a Xilinx AFX FF1152 Virtex-II Pro board with a xc2vp20 on it. I have tried to get a simple design up usign the SDRAM, but...

Hi there, We have a Xilinx AFX FF1152 Virtex-II Pro board with a xc2vp20 on it. I have tried to get a simple design up usign the SDRAM, but the memory check code inserted by EDK fails (the code lives in the PLB BRAM, and EDK kindly included a memory checker for the SDRAM). On the FPGA I'm using one of the PPC cores, which is connected to some BRAM over the PLB, and to an SDRAM interface ...


NIOS SDRAM controller simulation

Started by Anonymous in comp.arch.fpga17 years ago

I'm trying to simulate a NIOS based system with a altera_avalon_new_sdram_controller which is shared with the systembus. When I try to do a...

I'm trying to simulate a NIOS based system with a altera_avalon_new_sdram_controller which is shared with the systembus. When I try to do a write (ST) to the SDRAM I see that the cpu.the_sdram_s1.sdram_s1_chipselect is asserted. However the NIOS top level cpu.zs_cs_n_to_the_sdram_sdram_chip is not. If I replace the SDRAM target address of the ST instruction with a different different t...


micron sdram module

Started by Steven in comp.arch.fpga17 years ago 5 replies

Hi, still sticked in the sdram controller project. I use a micron 256mb sdram following is its datasheet and simulation module's web...

Hi, still sticked in the sdram controller project. I use a micron 256mb sdram following is its datasheet and simulation module's web address : http://www.micron.com/products/DRAM/SDRAM/part.aspx?part=MT48LC16M16A2TG I now want to know whether a read or write successful or not. Can someone tell me which array of variable in micron's simulation module I should put in the "watch" ? Th...


read & write on SDRAM speed with PPC 300 MHz

Started by Pierre in comp.arch.fpga16 years ago 4 replies

Hello I use a Virtex-II Pro with PowerPC at 300 MHz, 8 kB IOCM, 32 kB DOCM and external 32 MB SDRAM (connected on PLB ) When I read 10...

Hello I use a Virtex-II Pro with PowerPC at 300 MHz, 8 kB IOCM, 32 kB DOCM and external 32 MB SDRAM (connected on PLB ) When I read 10 times 32 MB on my SDRAM, that takes 3.7'' and when I write the 320MB on the SDRAM it takes 9.6'' without burst support and 6" with burst support. Did someone knows why the read rate is 85 MByte/s and 53 MB/s(maximum ) for writing? Normally, with 6...


Xilinx user constraints with respect to output clock from the design

Started by gangireddy.p in comp.arch.fpga12 years ago 5 replies

Hi, Sdram signals are going out of my design to a SDR SDRAM. This SDR SDRAM requires a setup time of 3.8 ns. The clock to SDRAM is provided by...

Hi, Sdram signals are going out of my design to a SDR SDRAM. This SDR SDRAM requires a setup time of 3.8 ns. The clock to SDRAM is provided by the design which is generated from the DCM with the source clock at 40 Mhz. I tried to put output constraints on other SDRAM control signals with respect to the clock generated in the design(to meet the setup time of SDRAM). But it is showing error as we...


FIFO design

Started by Simone Winkler in comp.arch.fpga17 years ago 9 replies

Hello! I want to build a FIFO for a special purpose: I've got a microcontroller that interfaces to a SDRAM via an SDRAM-interface. The...

Hello! I want to build a FIFO for a special purpose: I've got a microcontroller that interfaces to a SDRAM via an SDRAM-interface. The microcontrollers data width is 16 bit while the SDRAM-interface needs 32 bit (if i write something to the sdram, in the first clock cycle, the interface needs the bank, row and column address (32 bit) and in the second clock cycle the data (only 16 bit, the...


Altera SDRam ip core

Started by Nick in comp.arch.fpga16 years ago

Hello, I interface my Cyclone with a micron SDRam using the Altera SDR SDRAM Controller but it seems that there is something very wrong in...

Hello, I interface my Cyclone with a micron SDRam using the Altera SDR SDRAM Controller but it seems that there is something very wrong in what I do. When I send a write command to the controller, what I get on the output using SignalTap is the write command issued to the SDRAM, but only 2 clocks later come the data. So the first two word I read are wrong, and the last two I write are l...


Addressing DDR-RAM

Started by Thomas in comp.arch.fpga15 years ago 2 replies

Hello, I've got a Xilinx Virtex 4 FPGA and would like to address the onboard DDR-SDRAM. I've found out that I can instantiate special DDR-IO...

Hello, I've got a Xilinx Virtex 4 FPGA and would like to address the onboard DDR-SDRAM. I've found out that I can instantiate special DDR-IO flip flops by hand (and found an example in the ISE-Webpack documentation). But I'm still not sure how to address the DDR-SDRAM best, especially I don't know how to handle the DQS-Signal of the DDR-SDRAM, because I need a sensitivity on both edges....


SDRAM Reading problem

Started by raju_lingala in comp.arch.fpga15 years ago

Hi all, I am new to this group and i am facing one problem regarding reading from the sdram. Actually I am accessing sdram indirectly through...

Hi all, I am new to this group and i am facing one problem regarding reading from the sdram. Actually I am accessing sdram indirectly through CPU. So I am writing write data into the fpga registers and set the wr_start bit, after completing the write operation wr_start bit will be cleared indicating write has completed. To verify the data written to sdram i am setting the read_start and reading i...