adding SDRAM to the S3 starter kit

Started by Simon in comp.arch.fpga16 years ago 5 replies

Hi all, I'd like to create a plugin for the S3 starter kit board that adds (say) 32 or 64 MBytes of SDRAM via ports A1 and A2. Not having...

Hi all, I'd like to create a plugin for the S3 starter kit board that adds (say) 32 or 64 MBytes of SDRAM via ports A1 and A2. Not having much experience using (for me, at least) such high frequency parts I was wondering if it was even possible... I'd like to run the microblaze processor synchronously, so clock frequency will be ~87MHz. I was thinking of using plain jane SDRAM not ...


Problem with connecting higher order address lines of SDRAM to FPGA

Started by Amirtham in comp.arch.fpga14 years ago 7 replies

Hi I have done a SDRAM controller design in spartan. using Micron SDRAM(128Mx32 with 4 banks). If I access SDRAM using address lines sdr_A8...

Hi I have done a SDRAM controller design in spartan. using Micron SDRAM(128Mx32 with 4 banks). If I access SDRAM using address lines sdr_A8 to sdr_A0, I am able to access one row 100% correct without error. My problem starts if I connect sdr_A11, sdr_A10, sdr_A9. Board hangs. I am not able to detect the board. Some how I used a tristate buffer for sdr_A10 (which is not the way to do so, b...


Spartan 3e and SDRAM

Started by Alex Freed in comp.arch.fpga13 years ago 4 replies

I'm planning to use Spartan 3e and SDRAM for a product - sort of a simple video "card" for an embedded CPU system. I got myself the Spartan...

I'm planning to use Spartan 3e and SDRAM for a product - sort of a simple video "card" for an embedded CPU system. I got myself the Spartan 3e STARTER kit and I'm trying to use the SDRAM on board. Found the MIG 1.6 and the pre-configured "bl2cl2" set of files. Got them to synthesize by editing a full (wrong for me) path to "params" file. So far so good. Changed the UCF to use the 50 MHz ...


using a SDRAM FIFO

Started by adrian in comp.arch.fpga16 years ago 3 replies

Hi there, I'm working on a packet analyzer on a Virtex2Pro xc2vp7 FPGA using Microblaze soft-core. My intention is to save packets recieved...

Hi there, I'm working on a packet analyzer on a Virtex2Pro xc2vp7 FPGA using Microblaze soft-core. My intention is to save packets recieved from the network in SDRAM for later process. I have been thinking of using a SDRAM FIFO to be able to process the packets after been saved in memory. As I am working with EDK 6.3 I was thinking of using a FIFO IP core to be used in SDRAM. Can th...


Measuring DDR SDRAM

Started by Anonymous in comp.arch.fpga16 years ago

Hi, maybe someone has had any experience on the following problem: I am searching for guidelines on measuring data lines, strobe...

Hi, maybe someone has had any experience on the following problem: I am searching for guidelines on measuring data lines, strobe lines, control lines between DDR SDRAM and user FPGAs (DDR SDRAM controller) on the board but unfortunately I have not found such information yet. I would like to know what I have to take into account when trying to measure with an oscilloscope the different...


SDRAM HOW?

Started by fahadislam2002 in comp.arch.fpga16 years ago 4 replies

Hi... I am trying to use SDRAM (not chip but SDRAM as in PCs)of micron in one of my projects (Gaming Console).IActually i want to use it to...

Hi... I am trying to use SDRAM (not chip but SDRAM as in PCs)of micron in one of my projects (Gaming Console).IActually i want to use it to use it as Shared Ram (As video and also for other purposes )... I have designed its controller and have checked by simulation...but here is a problem to use it... [b:8737ae6c30] Problem [/b:8737ae6c30]is that my [b:8737ae6c30]FPGA board donot ...


Synchronous clocking between Cyclone III and SDRAM

Started by jean-francois hasson in comp.arch.fpga12 years ago 11 replies

Hi, We are looking at interfacing the Cyclone III EP3C40 with an SDRAM at 90 MHz. We are considering having the FPGA generate the clock to...

Hi, We are looking at interfacing the Cyclone III EP3C40 with an SDRAM at 90 MHz. We are considering having the FPGA generate the clock to the interface and find a way to ensure both the sdram and the cyclone III are in phase regarding the clock. We could not find up to now a mechanism that would ensure that both the SDRAM and the cyclone III will have their clock almost with the sam...


DDR SDRAM simulation model, ML300, Infineon

Started by chakra in comp.arch.fpga14 years ago 6 replies

Hello all, I m working on an application using DDR SDRAM and i want to simulate (timing simulation) the DDR SDRAM working along with the...

Hello all, I m working on an application using DDR SDRAM and i want to simulate (timing simulation) the DDR SDRAM working along with the module i have created. the DDR SDRAM which is implemented on my board (ML300) is Infineon HYB25D256800AT-7. it is implemented as 4 discrete parts each 256Mbit as 8bits*32million = 32MB thus totalling 4*32MB= 128MB. if someone has the model/know a place w...


Sdram controller on the Altera Cyclone board!

Started by kingkang in comp.arch.fpga16 years ago 1 reply

Hi I wrote a sdram controller which has pass the RTL simulation. But when it come to the Altera cyclone board,the read/write data were wrong.I...

Hi I wrote a sdram controller which has pass the RTL simulation. But when it come to the Altera cyclone board,the read/write data were wrong.I have written sdram with some data,and then I read the data from sdram.But found the data is not equal to what have been written into the sdram.One or Some bits have wrong.It is random bit error!I don't know what's wrong.About the clock? or board dela...


How much time margin should I give to a SDRAM interface via FPGA?

Started by news reader in comp.arch.fpga14 years ago 3 replies

My altera FPGA is connected to a SDRAM on the prototype board. Assume the clock frequency is 100MHz, how much margin should I give to the SDRAM?...

My altera FPGA is connected to a SDRAM on the prototype board. Assume the clock frequency is 100MHz, how much margin should I give to the SDRAM? 3ns? 5ns?


MPMC2: MPMC2 with DDR2 SDRAM

Started by zyan in comp.arch.fpga14 years ago 17 replies

Hi, Has anyone successfully used MPMC2 as the memory controller for DDR2 SDRAM? I used it to interface with the Micron's MT47H32M16CC-37EB DDR2...

Hi, Has anyone successfully used MPMC2 as the memory controller for DDR2 SDRAM? I used it to interface with the Micron's MT47H32M16CC-37EB DDR2 SDRAM and it doesn't work. Any important steps/settings required in order to get it working? Thanks.


failed to write to SDRAM

Started by qudhs in comp.arch.fpga16 years ago 1 reply

Hi! does anyone have some experience with the Xilinx EDK OPB_SDRAM controller? I am using it to control an 8Mx32 external SDRAM (from Micron)....

Hi! does anyone have some experience with the Xilinx EDK OPB_SDRAM controller? I am using it to control an 8Mx32 external SDRAM (from Micron). It appears that not all the writing are done correctly. for some address space, there is no data or wrong data written to the SDRAM. in fact, the "wrong" writing happens periodically, as following, 1c, 1d, 1e,1f, 20,21,22,23,28,29,2a,2b (round 1) 5c...


VHDL CODE FOR SDRAM IN SPARTAN 3E

Started by Pablo in comp.arch.fpga14 years ago 3 replies

Does anyone try to read values from sdram without the use of Microblaze?. It is simple to read/write values in ddr sdram with the use of pointer...

Does anyone try to read values from sdram without the use of Microblaze?. It is simple to read/write values in ddr sdram with the use of pointer in MIcroblaze but how can you read values in vhdl code for displaying an image (store in sdram) with the use of a vga core.


Increase Memory Resource in SDRAM.

Started by Pablo in comp.arch.fpga14 years ago 5 replies

Hi, I have a project with a big requeriment of memory. So I have decided to generate a linker script with every section to SDRAM. The problem is...

Hi, I have a project with a big requeriment of memory. So I have decided to generate a linker script with every section to SDRAM. The problem is that I don't know how can I increase the "default memory area" for my app. The reason is that I do "xil_calloc", but when I put a big number I receive an error and I think I could do it in a Sdram with 32Mb. How can I increase the resources of my Sdr...


ISE 6.3 sp3 - PAR result strange

Started by Anonymous in comp.arch.fpga16 years ago

I have a top level schematic includes several macro instants (SDRAM controllers and others stuff) the design target spartan3-1000, speed-4. So far...

I have a top level schematic includes several macro instants (SDRAM controllers and others stuff) the design target spartan3-1000, speed-4. So far I haven't constraint pin LOC yet, but the SDRAM clock is constrainted at 166 Mhz. It's strange if I let the ISE "auto assign" the Inst. name as XLXI_xxx... for the the macros (specially the sdram controllers) then it pass 166 MHZ easily. If I manually a...


SDRAM Controller

Started by George in comp.arch.fpga18 years ago 7 replies

Hi! I am a bit new to FPGAs, so far I have only worked with CPLDs ( Xilinx 9500 family ). Now I would like to use a Spartan 2E ( with WebPack...

Hi! I am a bit new to FPGAs, so far I have only worked with CPLDs ( Xilinx 9500 family ). Now I would like to use a Spartan 2E ( with WebPack 5.2 and VHDL ) to make a SDRAM controller. I have searched this archive but I haven't found any topic related to my question. Here's the deal. When data needs to be transfered to the SDRAM the controller sends out data prior to generating the rising ...


external sdram and gdb tool

Started by Tom in comp.arch.fpga17 years ago 3 replies

Hi, I have some project where I store my entire program in the external sdram (by redirecting every section in the linker script to...

Hi, I have some project where I store my entire program in the external sdram (by redirecting every section in the linker script to the sdram). When I download the program to the board, it doesn't work. When I run the program in the debugger tool, it works. Does anybody know an answer to this problem ? regards, Tom


HELP!!! Interfacing Virtex-4 FPGA with SDR SDRAM

Started by Anonymous in comp.arch.fpga16 years ago 1 reply

Hello ALL, This is my second message :( I did not get answer for the first one, so I am sending it again. My be it got lost somewhere in...

Hello ALL, This is my second message :( I did not get answer for the first one, so I am sending it again. My be it got lost somewhere in news-server, or this is not the right NG to post this message. Any way, people here are talking about FPGA and SDRAM adn this is my current problem. I am having hard time designing the schematic to interface conventional SDRAM chip to Virtex-4 FPGA. As ...


how to speed up the program running in ddr sdram

Started by Athena in comp.arch.fpga15 years ago 3 replies

Hi all, At present, I am using Xilinx SPARTAN XC3S1500 FPGA with Micro MT46V16M16 to do some projects. As my programme is very large, there is...

Hi all, At present, I am using Xilinx SPARTAN XC3S1500 FPGA with Micro MT46V16M16 to do some projects. As my programme is very large, there is not enough space to put them in the bram, so I have to put them in the ddr sdram. However, I found that when the programme is in the ddr sdram, the speed is 20 times lower than in the bram. I couldn't endure it. Who knows how to speed up the programmi...


Altera Avalon Address format between Master & SDRAM controller?

Started by Anonymous in comp.arch.fpga16 years ago 1 reply

Hi there group, I'm implementing a user defined Master interface to the Avalon Bus using Altera's Stratix FPGA and read through the...

Hi there group, I'm implementing a user defined Master interface to the Avalon Bus using Altera's Stratix FPGA and read through the documentation on the Avalon Bus requirements and the SDRAM controller as a slave, and I'm still not quite getting how the SDRAM controller interprets an address supplied by a Master peripheral? The SDRAM has a total of 22 bits (12 bits row, 8 bits column,...