Xilinx EDK 10.1 - SDRAM access using MPMC/VFBC by peripheral

Started by Anonymous in comp.arch.fpga12 years ago 1 reply

Hello all, i try to make an accelerator that will share the SDRAM with Microblaze using a VFBC port on the MPMC. I use the Spartan 3E...

Hello all, i try to make an accelerator that will share the SDRAM with Microblaze using a VFBC port on the MPMC. I use the Spartan 3E Starter Kit and XPS 10.1. So, I created a core with the wizard, it has a FSL bus and I also created a VFBC bus too. For the first test, I try to write 32 bytes to the SDRAM when the processor sends a "1" through the FSL and verify the operation by reading...


SDRAM initialisation and MCF5272

Started by KBG in comp.arch.fpga15 years ago

Hi, According to the MCF5272 datasheet, and the schematic, the address line A22 and A23 of ColdFire are to be treated as SDBA0 and SDBA1...

Hi, According to the MCF5272 datasheet, and the schematic, the address line A22 and A23 of ColdFire are to be treated as SDBA0 and SDBA1 and connected to BA0 and BA1 of the SDRAM respectively. But when the register value is set according to the above, the SDRAM initialisation faces problem. But when i set a value in such a way that the address lines A23 and A24 of ColdFire are connec...


64-bit SODIMM module on 32-bit SDRAM-controller?

Started by Marc in comp.arch.fpga17 years ago

Hello, how do I connect a 64-bit wide SODIMM-SDRAM-module to a 32-bit SDRAM-controller? I saw different ways in the web (from connecting...

Hello, how do I connect a 64-bit wide SODIMM-SDRAM-module to a 32-bit SDRAM-controller? I saw different ways in the web (from connecting the upper and lower 32-bit together on the pcb and making the selection with the 8 dqm lines to very strange connections of the address lines to the dqm pins and different chip select) but have no idea which one is really working and the best way. I a...


SDRAM in EDK

Started by mvetromille in comp.arch.fpga16 years ago 4 replies

Hello! I instantiated SDRAM memory in an EDK project, but I don't know what I have to do in order to boot from it. I want to store my...

Hello! I instantiated SDRAM memory in an EDK project, but I don't know what I have to do in order to boot from it. I want to store my instructions and data into it. Does anyone can help me? Thank you! Melissa


running microblaze from bram through OPB-bus

Started by Frank van Eijkelenburg in comp.arch.fpga16 years ago 4 replies

Hi, We have a design with a microblaze which runs from bram at startup (connected through the LMB bus). After startup it is possible to...

Hi, We have a design with a microblaze which runs from bram at startup (connected through the LMB bus). After startup it is possible to download an application to sdram (connected through the OPB bus) and run from sdram. Since we are going to change the fpga type and get a lot more brams available; we are thinking to remove the sdram (to reduce costs) and replace it by bram. My que...


problems with verilog SDRAM models

Started by wallge in comp.arch.fpga14 years ago 9 replies

I am trying to write an SDRAM controller in VHDL for a mobile SDR SDRAM that I want to be able to control via an FPGA on the same PCB. I am...

I am trying to write an SDRAM controller in VHDL for a mobile SDR SDRAM that I want to be able to control via an FPGA on the same PCB. I am having trouble with the verilog model. I have used both a samsung and a micron model for the part (two compatible parts). Unfortunately these models are not available in VHDL, and my verilog is pretty weak. I wondered if any one had some experience with...


Using DDR SDRAM as single data rate ..?

Started by Anonymous in comp.arch.fpga13 years ago 8 replies

Is it possible to use DDR SDRAM as single data rate SDRAM and thus eliminate the need for DCM's and tight clock frequency specifications...

Is it possible to use DDR SDRAM as single data rate SDRAM and thus eliminate the need for DCM's and tight clock frequency specifications ..? The idea is to ignore the data sent on the second flank, and the timings associated with the DLL. The price is ofcourse half the datacapacity and half the speed. But the benefit is less complicated setup.


Memory Resource in SDRAM

Started by Anonymous in comp.arch.fpga14 years ago

Hello, my question is the following: I have created an application created in SDRAM in which I do "xil_malloc(16*4096)". The problem is that...

Hello, my question is the following: I have created an application created in SDRAM in which I do "xil_malloc(16*4096)". The problem is that it seems like there is not memory sufficient for my application. I have increased "HEAP_SIZE" and "STACK_SIZE" but I suppose that these parameters are not the problem. My sdram is 32Mb so I think I have enough memory for this requeriments. What can I ...


SDRAM vs DDR2 on Spartan3E

Started by Guru in comp.arch.fpga14 years ago 1 reply

Hi all, I am considering to replace a SDRAM with a DDR2 on a custom Spartan3E1200 board to gain some bandwidth in a Microblaze...

Hi all, I am considering to replace a SDRAM with a DDR2 on a custom Spartan3E1200 board to gain some bandwidth in a Microblaze system. Currently I am working with OPB_SDRAM core and I am not satisfied with 60MB bandwidth in burst mode (x16 SDRAM and 50MHz clock). It takes 4 cyles to read a word (32bits) and it does not support async clocking, so OPB clock is the same as RAM clock. I wonde...


Sharing SDRAM on Stratix II DSP Development kit

Started by Anonymous in comp.arch.fpga16 years ago

I would like to implement a design that shares the external SDRAM that is installed on the Stratix II DSP Development Kit board between the Nios...

I would like to implement a design that shares the external SDRAM that is installed on the Stratix II DSP Development Kit board between the Nios II controller and custom circuitry that will occupy a portion of the remaining Stratix II LE's (ALM's). Half of the SDRAM would be dedicated for collecting interleaved 8-bit data samples between the two on-board A/D's. Four of the 8-bit data samp...


large data access to SDRAM at fixed frequency

Started by mpierrotb in comp.arch.fpga15 years ago 3 replies

Hi ! I am new in electronique. I want to make an analog acquisition board with an ARM microcontroler ( Samsung S3C44B0x 66MHz) with a 8Mbytes...

Hi ! I am new in electronique. I want to make an analog acquisition board with an ARM microcontroler ( Samsung S3C44B0x 66MHz) with a 8Mbytes SDRAM and an A/D converter( Analog AD775 ). The sampling rate of the A/D converter is at 30Mhz, and i would like to connect its digital output to the S3c44b0x data bus by using the DMA of the uC. Data sent by the ADC will be wrote to the SDRAM by usi...


ddr2 sdram xilin mig controller, mig v1.72 issue

Started by Anonymous in comp.arch.fpga13 years ago

Hi, I am a design engineer, i have avnet xcv5lx110t board, it has a ddr2 sdram (mt47h14m16bg-5e, micron) attached, xilinx provides its...

Hi, I am a design engineer, i have avnet xcv5lx110t board, it has a ddr2 sdram (mt47h14m16bg-5e, micron) attached, xilinx provides its MIG controller, i installed mig v1.72 , and generated a ddr2 sdram controller, with data width 32, with its provided test bench. when i simulated the design with modelsim 6.1e, there were compiler errors that showed " data_dq runs out of its bounds", ...


SRAM to be able to Read/Write SDRAM

Started by Vick in comp.arch.fpga16 years ago

Hello All, I have questions regarding a project i am currently working on. I have been assigned to develop an SRAM interface to be able...

Hello All, I have questions regarding a project i am currently working on. I have been assigned to develop an SRAM interface to be able to Read/Write an SDRAM (Micron 168-pin).And the SRAM should maintain its own functonality i.e. the SRAM itself can be read/written. Also, whatever data is read from SDRAM should be stroed in SRAM. I am following the XAPP134 article and another free IP fro...


Preloading SDRAM?

Started by Subhasri krishnan in comp.arch.fpga16 years ago 7 replies

Hi, I have to initialise an SDRAM with an LUT (48MB). I have the LUT in .dat format. Is there anyway I can do this with the Xilinx ISE tool?...

Hi, I have to initialise an SDRAM with an LUT (48MB). I have the LUT in .dat format. Is there anyway I can do this with the Xilinx ISE tool? I can do writes continuously but I'd like to know how to access the file in the first place. I read somewhere that I need a different IDE for it..that too only for RAM blocks. what does that mean? I am new to this field so if this question has been as...


fifo or sdram bug?

Started by kaz in comp.arch.fpga6 years ago 30 replies

In our system a signal is passed through a couple of fifos inside FPGA and then onto external sdram to be read by application software. All looks...

In our system a signal is passed through a couple of fifos inside FPGA and then onto external sdram to be read by application software. All looks ok except that some units in the field show occasional errors in that signal read from sdram. The error is as follows: odd samples are offset by 8 samples from the even. So if we remove this offset then signal looks ok. I can't reproduce the error in ...


Problem when for program and data memory use SDRAM

Started by axalay in comp.arch.fpga13 years ago 1 reply

I have a PowerPC (Virtex2PRO) and SDRAM (programm and data memory). I anderstand that the bootloader may be use to load programm from systemACE...

I have a PowerPC (Virtex2PRO) and SDRAM (programm and data memory). I anderstand that the bootloader may be use to load programm from systemACE or FLASH Memory. But I whant load programm from configurePROM to SDRAM. Is it possible? Somebody help me?


debug application in sdram (microblaze system)

Started by Frank van Eijkelenburg in comp.arch.fpga17 years ago 3 replies

Hi, Is it possible to debug an application which is in sdram by use of xmdstub? I have a small bootloader program which programs a final...

Hi, Is it possible to debug an application which is in sdram by use of xmdstub? I have a small bootloader program which programs a final application into sdram (by use of xmodem). Now I want to debug this application, is that possible or should I use the opb mdm device?! If it's possible, I guess I have to build a bootloader with the xmdstub and make a connection. But how to get my applica...


EMC/SDRAM

Started by ram in comp.arch.fpga18 years ago

Hi, Whats the difference between IPs OPB_sdram/PLb_sdram and OPB_EMC/PLB_EMC. When I will make a choice between EMC/SDRAM. If i have a...

Hi, Whats the difference between IPs OPB_sdram/PLb_sdram and OPB_EMC/PLB_EMC. When I will make a choice between EMC/SDRAM. If i have a onboard SRAM, can i still choose a EMC core. I would appreciate your time and effort you spend to answer. Thankyou RAm


SRAM to be able to read/write Micron SDRAM

Started by Vick in comp.arch.fpga16 years ago 5 replies

Hello all, I had psted this question earlier but havent got any response yet... I was wondering if the questions I asked made any sense (or)...

Hello all, I had psted this question earlier but havent got any response yet... I was wondering if the questions I asked made any sense (or) were they just out of the way... So again, I have the Micron SDRAM Verilog code and I need to make SRAM read/write the SDRAM... Obviosuly, the SRAM shold maintain its own functionality (i.e. it itself can be read/written). The questions I have are...


DDR SDRAM access with MPMC2, Databus Width

Started by Mack in comp.arch.fpga15 years ago 6 replies

Hi all, I'm working on a Virtex-4 FX12LC Design with PPC405 Core, SDRAM and Multiport Memory Controller 2 (MPMC2 release 2006/08/31). The...

Hi all, I'm working on a Virtex-4 FX12LC Design with PPC405 Core, SDRAM and Multiport Memory Controller 2 (MPMC2 release 2006/08/31). The Memec Development Board contains the Infineon DDR SDRAM HYB25D512160BC-6 (64 Mbyte, Databus 16 bit). I started the Design with BSB and OPB_DDR_CNTLR, then replaced the DDR_CNTLR with the MPMC2 Core of from "ml403_ddr_p_100mhz" and changed the Memory Widt...