Xilinx DDR SDRAM Controller

Started by Remis Norvilis in comp.arch.fpga15 years ago 1 reply

I am having a difficulty grasping project structure, generated by Xilinx MIG007 software. I?ve generated 16-bit data DDR1 SDRAM interface to...

I am having a difficulty grasping project structure, generated by Xilinx MIG007 software. I?ve generated 16-bit data DDR1 SDRAM interface to Spartan3 xc3s500-4-efg208 device. MIG user manual describes user signal interface and timing for ddr1_top which is the main DDR SDRAM controller. But it?s hierarchically below ddr1_test and mem_interface_top modules. These probably enhance user interfa...


Spartan 2E and SDRAM

Started by smu in comp.arch.fpga16 years ago 1 reply

Hello, I want to connect a SDRAM (single data rate) to a spartan 2e FPGA. Are there some special recommendations about the attribution of the...

Hello, I want to connect a SDRAM (single data rate) to a spartan 2e FPGA. Are there some special recommendations about the attribution of the pins? Thank you in advance smu


FIFO in SDRAM

Started by sjulhes in comp.arch.fpga15 years ago 11 replies

Hello, We need to implement a FIFO using an SDRAM within a V2PRO. I guess this function already exists, so does someone has...

Hello, We need to implement a FIFO using an SDRAM within a V2PRO. I guess this function already exists, so does someone has links, information.... ??? Thank you St?phane.


Opencores DDR2 SDRAM controller with spartan3e starter board

Started by blinkenlights in comp.arch.fpga13 years ago 5 replies

Ok, tried it for weeks, now I give up and ask for help... I have a Spartan S3E starter kit board with a 46V32M16 DDR2 SDRAM on it. My design...

Ok, tried it for weeks, now I give up and ask for help... I have a Spartan S3E starter kit board with a 46V32M16 DDR2 SDRAM on it. My design needs to read and write 32 bit words to SDRAM. I tried MIG 2.2 from the Xilinx coregen tools, but couldn't get it to work. Finally I found a controller design originally written by Markus Lemke and then modified for the Spartan S3E by David Ashley at Ope...


DDR_SDRAM_VHDL_models

Started by Anonymous in comp.arch.fpga14 years ago 2 replies

Does anynone know where can I find VHDL models for DDR-I SDRAM modules? I have an XUP board and I want to run some simulations before downloading...

Does anynone know where can I find VHDL models for DDR-I SDRAM modules? I have an XUP board and I want to run some simulations before downloading my design to the FPGA. I am not looking for a specific model. Any generic DDR-I SDRAM model will do the job.


SDRAM

Started by Fayette in comp.arch.fpga16 years ago 1 reply

Hello, I have instanced a generic sdram controller for a MicroBlaze on a Spartan 3. The problem is that the refresh is not functioning. The...

Hello, I have instanced a generic sdram controller for a MicroBlaze on a Spartan 3. The problem is that the refresh is not functioning. The memory buss is totally quiescent except when reads or writes are occurring. Is there is some initialization command or signal I am overlooking. Thanks, Fayette


Finding DDR SDRAM SODIMM(200 pin) socket.

Started by SeungHeun, Lee in comp.arch.fpga16 years ago 1 reply

Hello, To interfacing DDR memory module to memory controller, I'm finding DDR SDRAM SODIMM socket. (Not memory module). I tried to search...

Hello, To interfacing DDR memory module to memory controller, I'm finding DDR SDRAM SODIMM socket. (Not memory module). I tried to search serveral socket & connector vendors like MOLEX, AMP. , but only SDRAM SODIMM and DDR DIMM are available in their catalog. Does anyone know the vendor and part number? Regards, S.H, Lee


SDRAM Controller

Started by maxascent in comp.arch.fpga14 years ago 1 reply

Hi I have designed an SDRAM controller and nearly ready to synth and P&R. My question is do I need to add any offset constraints to the ucf?...

Hi I have designed an SDRAM controller and nearly ready to synth and P&R. My question is do I need to add any offset constraints to the ucf? I see that the Xilinx XAPP134 uses them but the newer DDR designs which are generated using MIG do not. Any info would be appreciated? Cheers Jon


Multichannel Opb Memory Controller question

Started by Marco T. in comp.arch.fpga15 years ago 9 replies

Hallo, I would develop a system based on opb multichannel memory sdram controller. I would connect Microblaze to the controller using xcl and...

Hallo, I would develop a system based on opb multichannel memory sdram controller. I would connect Microblaze to the controller using xcl and not opb bus. I would also connect an external microcontroller to sdram: I thought to create a custom opb master peripheral and connect it to opb bus. The opb bus will have a master (the external micro) and a slave (the sdram). Is it reliable? ...


DDR SDRAM controller

Started by subint in comp.arch.fpga15 years ago

Hello guys.. Please anyone help me get a ddr sdram controller for the v4lx60 board. Is the Mig tool is enough. thanks in advance

Hello guys.. Please anyone help me get a ddr sdram controller for the v4lx60 board. Is the Mig tool is enough. thanks in advance


Virtex-II Pro and DDR2 SDRAM differential IO

Started by bob in comp.arch.fpga17 years ago

I'm doing a Virtex-II Pro design that uses DDR SDRAM SODIMM modules as data storage. There's a possibility (because DDR and DDR2 SODIMMs...

I'm doing a Virtex-II Pro design that uses DDR SDRAM SODIMM modules as data storage. There's a possibility (because DDR and DDR2 SODIMMs are footprint compatible) to support the upcoming DDR2 modules in this design too. Now, there's a problem: DDR2 SDRAM supports the use of differential signaling on data strobe lines (DQS). However, these signals are still 1.8V SSTL. Virtex-II Pro device (...


SDRAM controller selection

Started by pinku in comp.arch.fpga15 years ago 1 reply

Hello grps, Can you tell me what is the basis for selecting the DDR controller? For example i have a micron DDR SDRAM and i have to see if it...

Hello grps, Can you tell me what is the basis for selecting the DDR controller? For example i have a micron DDR SDRAM and i have to see if it compatible with the DDR controller which is within network processor. Wht all parameter should i check? Please let me know that Regards Praveen


sdram core in EDK

Started by tort...@yahoo.com in comp.arch.fpga16 years ago

Hello all: I am sorry for troubling you for something this trivial, but I am new to EDK. I have instanced a generic sdram controller for a...

Hello all: I am sorry for troubling you for something this trivial, but I am new to EDK. I have instanced a generic sdram controller for a MicroBlaze on a Spartan 3. The problem is that the refresh is not functioning. The memory buss is totally quiescent except when reads or writes are occurring. I am sure there is some initialization command or signal I am overlooking. Thanks, Faye...


DMA on Virtex-4 using PPC

Started by Harry Stello in comp.arch.fpga15 years ago 1 reply

Hello, I need to create a custom peripheral that DMA's data to the DDR SDRAM on the ML403 board. My custom componet & the DDR SDRAM reside...

Hello, I need to create a custom peripheral that DMA's data to the DDR SDRAM on the ML403 board. My custom componet & the DDR SDRAM reside on the PLB bus. Does anybody have an example of how to do this? The template that XPS generates does not provide any details and as everyone knows, the xilinx documentation is pretty poor. Thanks in advance Harry


How does a SDRAM controller work?

Started by jeffsen in comp.arch.fpga16 years ago 5 replies

Dear all, Normally SDRAM needs tens of MS to refresh bank of memory,while what happens when I happened to visit this memory address,either read or...

Dear all, Normally SDRAM needs tens of MS to refresh bank of memory,while what happens when I happened to visit this memory address,either read or write. Dose the SDRAM controller(say,IP core from Xilinx) makes this read/write operation waiting for this refresh period and execute read/write command afterwards(That's unacceptable in term of time or speed for this read/write operation!)? Or it handl...


Xilinx Microblaze SDRAM burst access

Started by Dirk Ziegelmeier in comp.arch.fpga17 years ago 1 reply

Hello Group, I'm currently evaluating a Xilinx Microblaze system. One of the must-have features is a fast memcopy. Therefore, I implemented a...

Hello Group, I'm currently evaluating a Xilinx Microblaze system. One of the must-have features is a fast memcopy. Therefore, I implemented a basic system consisting of a Microblaze core (no caches, but program runs in BlockRAM) and a SDRAM controller. Burst support of the SDRAM core is enabled. Burst support of the microblaze core should work out-of-the-box according to the manuals. The ...


Error using SOPC builder - "Custom SDRAM" with 8-bits gives error with Signal "az_be_n"

Started by Anonymous in comp.arch.fpga14 years ago 1 reply

I'm trying to make a SDRAM controller with SOPC builder, but when I change the data width to 8bits I get the following error.. Warning: Signal...

I'm trying to make a SDRAM controller with SOPC builder, but when I change the data width to 8bits I get the following error.. Warning: Signal "az_be_n" of type "byteenable_n" and width 1 must have width of 2, 4, 8, 16, 32, 64, 128. I'm trying to make the system for a 64Mb SDR SDRAM, Micron MT48LC8M8A2P-75. Even when I select the Alliance AS4LC2M8S0-10 chip it does the same thing. So ...


sharing sdram and parallel nor flash address/data bus using xilinx edk

Started by john1529 in comp.arch.fpga12 years ago 1 reply

The custom board that I am working on has a SDRAM and parallel NOR- FLASH, and they share the same address and data I/0 pins in the FPGA. SDRAM...

The custom board that I am working on has a SDRAM and parallel NOR- FLASH, and they share the same address and data I/0 pins in the FPGA. SDRAM uses mpmc controller and FLASH uses xps_mch_emc controller. Since they use different memory controllers I need to implement some logic in order to multiplex signals that come from the controllers to the external pins. Data buses are bidirectional whi...


DDR SDRAM on ML401

Started by al99999 in comp.arch.fpga15 years ago

Has anybody managed to use the MiG to generate a controller for the DDR SDRAM on the Xilinx ML401 board? The RAM (infineon) on the board is not...

Has anybody managed to use the MiG to generate a controller for the DDR SDRAM on the Xilinx ML401 board? The RAM (infineon) on the board is not one of the listed options (they are all micron). Thanks, Alastair


ddr sdram controller

Started by Anonymous in comp.arch.fpga14 years ago 5 replies

How can I get a ddr sdram controller for the MT46V16M16TG -75 micron chip. I want a controller without the plb or opb interface. I tried...

How can I get a ddr sdram controller for the MT46V16M16TG -75 micron chip. I want a controller without the plb or opb interface. I tried open cores.org but it says that the repository is empty with no files pertaining to the ddrsdram controller core. Could someone give me right pointers? Thanks, D.