DDR SDRAM configuration

Started by Anonymous in comp.arch.fpga16 years ago

Hi, I have programmed my FPGA with an evaluation bitstream file for DDR-SDRAM controller. When measuring bank address bit 0 I can see...

Hi, I have programmed my FPGA with an evaluation bitstream file for DDR-SDRAM controller. When measuring bank address bit 0 I can see that it does not get '1' during initialization phase. That means that EXTENDED mode register is never written to that is the DLL is not enabled. But the evaluation design seems to work. So how can that be ? Rgds Andr=E9


SDRAM Controller

Started by Grey Beard in comp.arch.fpga15 years ago 3 replies

I'm quite new to this area..I'm completeing a bachelor in electronics..As a part of my project i'm to create a sdram controller for xilinx 11...

I'm quite new to this area..I'm completeing a bachelor in electronics..As a part of my project i'm to create a sdram controller for xilinx 11 pro(ff1152) based memec board...Although memory managent is available as a ref design..We are not using the power processor inside?Can anyone give me some directions on this one?i'd be grateful..


sdram modeling

Started by Andy Luotto in comp.arch.fpga15 years ago

Hi there I am using a Micron verilog behavioaral mdoel for SDRAM MT48LC16M16A2 which is rated for CL=2 and I want to adapt the timings to...

Hi there I am using a Micron verilog behavioaral mdoel for SDRAM MT48LC16M16A2 which is rated for CL=2 and I want to adapt the timings to verify a Mobile RAM which provides timings (tCK3, tAC3 etc.) for CL=3. How can I do it safely? Thanks in advance to who'll reply task set_ _timing; begin // Special timing for -75, CAS Latency = 3, tAC = 7.4ns! tAC = 7.4;


About DDR SDRAM

Started by Gordon Freeman in comp.arch.fpga14 years ago 5 replies

Hi everyone! I'm working with DDR SDRAM but I don't know how to choose row address and column address. Can you help me, please?

Hi everyone! I'm working with DDR SDRAM but I don't know how to choose row address and column address. Can you help me, please?


DDR SDRAM in extended military applications

Started by fpgabuilder in comp.arch.fpga14 years ago

Hi, I am wondering what kind of issues I should look for when designing in DDR SDRAM for extended temperatures. For e.g. does temp....

Hi, I am wondering what kind of issues I should look for when designing in DDR SDRAM for extended temperatures. For e.g. does temp. compensated refresh cycles extend to ambient temperatures of -40 to +85 deg C and over? Any other interesting things that could happen? Thanks and best regards, -sanjay


can someone recommend a board?

Started by Subhasri krishnan in comp.arch.fpga15 years ago 7 replies

Hi all, After some hardware problems with our protoype I have been advised to use a board. But I cannot find one with all the features. 1) VGA...

Hi all, After some hardware problems with our protoype I have been advised to use a board. But I cannot find one with all the features. 1) VGA in and out ports 2) SDR SDRAM. I have looked at digilentinc and xess but these people dont have any that fits all requirements. I have the XUP V2P board with the video capture card and 256MB DDR SDRAM. How difficult will it be for me to use the DDR ...


OpenCore.org DDR SDRAM problems

Started by Yttrium in comp.arch.fpga17 years ago 1 reply

hey, i needed a ddr sdram controller for a MT46V16M16 so when i saw the IPCORE on OpenCores.org i thought why not use it ... so i have build...

hey, i needed a ddr sdram controller for a MT46V16M16 so when i saw the IPCORE on OpenCores.org i thought why not use it ... so i have build all the necessary controlling processes and blocks and simulated it and tried it out on a virtexII FPGA and worked fine, then i connected the DDR controller to it at i got this HUGE list of warnings about unconnected elements. (i attached it to this m...


SDRAM types and availability

Started by rickman in comp.arch.fpga18 years ago 2 replies

I was discussing SDRAM a few weeks ago and I can't seem to find it in this newsgroup. I guess it had gone to email. I have finally had...

I was discussing SDRAM a few weeks ago and I can't seem to find it in this newsgroup. I guess it had gone to email. I have finally had a chance to go on the web and take a look at some of the sources and I am finding information hard to come by. I only find four main companies making parts in either x32 arrangements or in small packages. They are Micron, Samsung, Elpida and Hynix. I know...


SDRAM Controller

Started by Grey Beard in comp.arch.fpga15 years ago

I'm quite new to this area..I'm completeing a bachelor in electronics..As a part of my project i'm to create a sdram controller for xilinx 11...

I'm quite new to this area..I'm completeing a bachelor in electronics..As a part of my project i'm to create a sdram controller for xilinx 11 pro(ff1152) based memec board...Although memory managent is available as a ref design..We are not using the power processor inside.The subsequent modules are in VHDL.Can anyone give me some directions on this one?i'd be grateful..


Noob quesion about SDRAM usage.

Started by Anonymous in comp.arch.fpga15 years ago 2 replies

Hello, I'm relatively new to FPGA programming and looking for some advice. I have an application that needs reliable, high bandwidth (+50...

Hello, I'm relatively new to FPGA programming and looking for some advice. I have an application that needs reliable, high bandwidth (+50 MHz), access to a few Megs worth of RAM and I am wondering how I should go about this. I am working with the Xilinx ML403 development board which has the Virtex-4 FX12 FPGA and 64 MB of DDR SDRAM. My intention is to implement my project as a periphera...


How to Connect User-Defined Master Peripheral to SDRAM Slave Peripheral in SOPC Builder

Started by Pino in comp.arch.fpga17 years ago

I developed a custom state machine design as a Master Peripheral using the Avalon Bus specifications. The purpose of this peripheral is...

I developed a custom state machine design as a Master Peripheral using the Avalon Bus specifications. The purpose of this peripheral is to read/write to external memory (i.e. SDRAM). I then include this in SOPC Builder as a User-Defined Logic and define it as a Master Peripheral and associate my top-level entity ports to the appropriate names for the Avalon Bus. When I include the SDRAM co...


DLL feedback delay

Started by steve in comp.arch.fpga16 years ago

I want to simulate a fpga-based SDRAM controller with a SDRAM model. Say the PCB delay is 1 ns, shall I delay the feedback clock with 1ns or...

I want to simulate a fpga-based SDRAM controller with a SDRAM model. Say the PCB delay is 1 ns, shall I delay the feedback clock with 1ns or 2ns (because of the round trip trace on the PCB)?


Xess' XSA-50 Audio Playback / SDRAM

Started by eric in comp.arch.fpga18 years ago

Hi All, Im trying to get audio playback from an XSA-50 and XST2 using the example code from the Xess website ("Audio project for the XSV...

Hi All, Im trying to get audio playback from an XSA-50 and XST2 using the example code from the Xess website ("Audio project for the XSV Board (Univ. of Queensland)") The only problem is, that particular example project uses an Xess board that has SRAM (The XSA-50 has SDRAM). No problem... just substitute the SDRAM controller example (also from the Xess website) and incorporate it in...


Good SDRAM Controller

Started by Peter Sommerfeld in comp.arch.fpga17 years ago 9 replies

Hi folks, Can anyone recommend an SDRAM controller, free or otherwise, with the following features: - synthesizable to > 100 MHz fmax on...

Hi folks, Can anyone recommend an SDRAM controller, free or otherwise, with the following features: - synthesizable to > 100 MHz fmax on Stratix -7 (preferably 133 MHz) - allows latent read bursts to maximum throughput - burtsts efficiently (keeps bank rows open where possible) For starters, I am looking at Rudolf Usselmann's controller from OpenCores but I'm concerned that the Wis


problem in interfacing with SDRAM controller

Started by Amirtham in comp.arch.fpga14 years ago

hi all, I have a core already inside the Spartan 3 FPGA. I m trying to integrate SDRAM Controller with the existing core. My board doesn't...

hi all, I have a core already inside the Spartan 3 FPGA. I m trying to integrate SDRAM Controller with the existing core. My board doesn't get detected at all after programming the spartan. Anyone help pls... Thanks!! Amirtha.


Spartan 3E starter kit DDR SDRAM

Started by fpgauser in comp.arch.fpga14 years ago 5 replies

I am relying to the older "Spartan 3E starter kit DDR SDRAM code Options" thread. Is there such a demo out, mentioned in the thread? I read...

I am relying to the older "Spartan 3E starter kit DDR SDRAM code Options" thread. Is there such a demo out, mentioned in the thread? I read in several groups that it is a problem to get this DDR Ram running ?


Implementing a reliable counter inside SDRAM memory mapped device

Started by valentin tihomirov in comp.arch.fpga17 years ago 2 replies

The idea is to read a stream of words from a single address location. This demands a mechanism to recognoze that a read cycle has finished. Is...

The idea is to read a stream of words from a single address location. This demands a mechanism to recognoze that a read cycle has finished. Is it possible? As far as I understand, SDRAM is an asynchronous device. However, 4-way handshaking is not used, so it is not possible to mark the end of transfer. Thanks.


I could run my program at DDR Sdram.

Started by Pablo in comp.arch.fpga13 years ago 3 replies

Hi, I have written already about this topic. At finally I have configured a DDR SDRAM core for PowerPC so I could read and write from/ to DDR....

Hi, I have written already about this topic. At finally I have configured a DDR SDRAM core for PowerPC so I could read and write from/ to DDR. It supports words, half words and bytes. I have probed it with Xilinx TestMemory and Mwr/Mrd in xmdstub. Everything works fine and I could use this memory for my programs. The problem is that my programs have growed a lot and now I have to download ...


DDR* SDRAM modules for simulation

Started by Aleksandar Kuktin in comp.arch.fpga6 years ago 6 replies

Hi all. Is there, somewhere, an open-source Verilog (or VHDL, but Verilog is preferred) module of a DDR1/2/3 SDRAM that can be used for...

Hi all. Is there, somewhere, an open-source Verilog (or VHDL, but Verilog is preferred) module of a DDR1/2/3 SDRAM that can be used for simulating a memory chip/module?? I want to build a memory controller, but want to do as much as possible in the simulator and hopefully only verify the correctness of it in silicon.


SDRAM sustained bursts

Started by Alex Ungerer in comp.arch.fpga16 years ago 7 replies

Hello, I am not sure if this is the right NG, but since it concerns memory driven by an FPGA, here goes. My question is about burst writes...

Hello, I am not sure if this is the right NG, but since it concerns memory driven by an FPGA, here goes. My question is about burst writes to SDRAM memory (be it standard, DDR or DDR2). Is it possible to sustain a burst write for an undefined number of words? Here is my setup: I have some incomming flow of data arriving at a constant speed of, say 250 MWords/s, which needs to be writ...