SPDIF receiver

Started by aravind in comp.arch.fpga11 years ago 9 replies

Hi Im planning to design an SPDIF receiver for implementation on Spartan 3 FPGA , But im not sure how to go about the design,Does any one...

Hi Im planning to design an SPDIF receiver for implementation on Spartan 3 FPGA , But im not sure how to go about the design,Does any one have ideas ? Thank u


Fpga eval. board with spdif receiver?

Started by David in comp.arch.fpga13 years ago

Does anybody know of an fpga eval. board (preferably with a xilinx part) that has a spdif receiver on board(like the cirrus cs8414 or cs8416)?...

Does anybody know of an fpga eval. board (preferably with a xilinx part) that has a spdif receiver on board(like the cirrus cs8414 or cs8416)? The higher fpga board seem to have stuff for video, but nothing for digital audio. Thanks, Dave


Fast Sampling of digital signals

Started by aravind in comp.arch.fpga10 years ago 7 replies

Hi, I'm building a S/PDIF Receiver for implementation on spartan 3 fpga. I don't have an expensive DSO to analyze the spdif signals : ( ...

Hi, I'm building a S/PDIF Receiver for implementation on spartan 3 fpga. I don't have an expensive DSO to analyze the spdif signals : ( So i decided to build a sampler and run it fast enough, say 10-20 times the spdif signal frequency and the display the signal on some audio editing software.(remember i'm sampling only digital signals so there's no ADC involved) So here's my setup,...


Looking for a simple SPDIF to I2S audio convertor IP.

Started by Aphraton in comp.arch.fpga4 years ago

Hello! I am looking for a simple shareware SPDIF to I2S audio convertor IP. I saw one in Opencores, but it is was actually AES/EBU-> I2S IP...

Hello! I am looking for a simple shareware SPDIF to I2S audio convertor IP. I saw one in Opencores, but it is was actually AES/EBU-> I2S IP overloaded with AES/EBU extraction options. --------------------------------------- Posted through http://www.FPGARelated.com


PLLs on biphase mark signals

Started by Adam in comp.arch.fpga13 years ago 6 replies

Hello all, Will an FPGA PLL lock onto a biphase mark(Manchester ??) encoded signal? I'm trying to build an SPDIF receiver and am wondering...

Hello all, Will an FPGA PLL lock onto a biphase mark(Manchester ??) encoded signal? I'm trying to build an SPDIF receiver and am wondering if its possible to directly connect the input signal(after analog level adjustment) to an FPGA and read the level at the 90 and 270 degree phases. If frames are continuously being transmitted when the PLL attempts to lock on, how does it know which f...