Control asynchronous SRAM like synchronous SRAM

Started by Michael Dreschmann in comp.arch.fpga12 years ago 3 replies

Hello, I've an Virtex II (later it'll be a Spartan 3) witch is connected to external asynchronous SRAM. Now I would like to access it in the...

Hello, I've an Virtex II (later it'll be a Spartan 3) witch is connected to external asynchronous SRAM. Now I would like to access it in the same way as a synchronous SRAM (like a BRAM for example). I think reading should work in the same way as with an synchronous SRAM (set address and /oe and read data at the next clock) as long the SRAM is fast enough. But I've no idea how to implement ...


SRAM to be able to Read/Write SDRAM

Started by Vick in comp.arch.fpga13 years ago

Hello All, I have questions regarding a project i am currently working on. I have been assigned to develop an SRAM interface to be able...

Hello All, I have questions regarding a project i am currently working on. I have been assigned to develop an SRAM interface to be able to Read/Write an SDRAM (Micron 168-pin).And the SRAM should maintain its own functonality i.e. the SRAM itself can be read/written. Also, whatever data is read from SDRAM should be stroed in SRAM. I am following the XAPP134 article and another free IP fro...


Prototyping board with 4+ MB SRAM?

Started by Anonymous in comp.arch.fpga14 years ago 3 replies

Hello, Does anyone happen to know of a stock FPGA prototyping board with (a) onboard oscillator, (b) Ethernet and (c) at least 4 MB of...

Hello, Does anyone happen to know of a stock FPGA prototyping board with (a) onboard oscillator, (b) Ethernet and (c) at least 4 MB of SRAM? I have a need for such a board in a configuration which needs to support a very large range of input frequencies, hence I would prefer using SRAM; however, most boards seem to have no more than 1 MB SRAM and the rest SDRAM... which would have to be ...


Problem with writing values to SRAM from XMD

Started by Roman in comp.arch.fpga10 years ago 2 replies

Hello! I am using a board with Virtex4 PPC405, external asynchronous SRAM memory and EDK 8.2i. If application program resides in BRAM and I...

Hello! I am using a board with Virtex4 PPC405, external asynchronous SRAM memory and EDK 8.2i. If application program resides in BRAM and I want to write and read from SRAM, it is only possible if there is instruction and data cache enebled and I add XCache_EnableCache in the beginning of the code. So far it works. Then I tried to run application from SRAM. So I generated linker script tel...


MicroBlaze & SRAM

Started by Ben G in comp.arch.fpga13 years ago 5 replies

I have an EDK design with a MicroBlaze processor and use the External Memory Controller (EMC) to get access to off-chip SRAM. I access the...

I have an EDK design with a MicroBlaze processor and use the External Memory Controller (EMC) to get access to off-chip SRAM. I access the SRAM from c using a pointer and have a loop in my program that writes a value and increments the pointer to the next address. As I am using a pointer to type integer it is increased by 4 locations each time I increment it. The SRAM I am accessing ho...


Can use SRAM instead of VRAM ......... how ???????????

Started by fahadislam2002 in comp.arch.fpga12 years ago 1 reply

Hi.. i wanna use sram instead of Vram in my project ... according t my knowledge vram is same as sram but its dual port...........as...

Hi.. i wanna use sram instead of Vram in my project ... according t my knowledge vram is same as sram but its dual port...........as fo display its needed to read and write at same time fastly ...so use dual port sram...... bu problem is ... i m available only sram which is no dual port.............is it possible to use it for display???????? and ...


PCB routing issues for sync SRAM

Started by radarman in comp.arch.fpga7 years ago 24 replies

This isn't strictly a FPGA question, but I figured someone here might be able to point me in the right direction. I am designing a board with...

This isn't strictly a FPGA question, but I figured someone here might be able to point me in the right direction. I am designing a board with an Altera EP3C40 in the 240-pin QFP and a Cypress CY7C1792 static SRAM in the 100 pin QFP. I would like to operate the SRAM at 200MHz, so I know the routing needs to be somewhat careful. (I'm internally "dual-porting" the SRAM, and each port needs to...


ML505 - How to read/write SRAM?

Started by charlie78 in comp.arch.fpga8 years ago 6 replies

Hi all, I'm an Italian student, I'm new in fpga and Microblaze implementation. I saw many starting tutorials about ML505 Xilinx Platform and usa...

Hi all, I'm an Italian student, I'm new in fpga and Microblaze implementation. I saw many starting tutorials about ML505 Xilinx Platform and usa of Xilinx Platform Studio 10.1 and EDK. In these tutorials I did not found any example of reading and writing operation of the SRAM. My code reside in BRAM and I would like to try to store some values in SRAM. By BSB I implemented SRAM in my system c...


Simulation MODEL for SRAM

Started by ALuPin in comp.arch.fpga13 years ago 2 replies

Dear Sir or Madam, I want to design an SRAM controller for the asynchronous SRAM IDT71V256SA. Can somebody tell me if there is such a VHDL...

Dear Sir or Madam, I want to design an SRAM controller for the asynchronous SRAM IDT71V256SA. Can somebody tell me if there is such a VHDL simulation model available? Thank you very much. Kind regards A.Vazquez G&D SystemDevelopment


Reading back SRAM content via JTAG?

Started by moe in comp.arch.fpga14 years ago 3 replies

I hope I'm posting it in the right groups. I've been designing for a while, but with minimal JTAG knowledge. Q: Can I use JTAG interface to...

I hope I'm posting it in the right groups. I've been designing for a while, but with minimal JTAG knowledge. Q: Can I use JTAG interface to verify what I wrote into the SRAM, instead of the traditional read-back method? My setup and the reason for wanting to do it this way is : An FPGA interfaces to a sync SRAM (QDR with separate write/read port). The FPGA can write to the SRAM using ...


Quality of timing simulation

Started by ALuPin in comp.arch.fpga13 years ago

Hello newsgroup users, I have made a timing simulation for my SRAM-Controller and an external asynchronous SRAM. I have used the FPGA...

Hello newsgroup users, I have made a timing simulation for my SRAM-Controller and an external asynchronous SRAM. I have used the FPGA Cyclone timing output file for my SRAM-Controller and the extra timing file for the SRAM model. Both components have been instantiated in a testbench. How reliable are such simulations? Where do come problems along with that kind of simulations ? ...


SRAM bidirectional bus

Started by ALuPin in comp.arch.fpga13 years ago 3 replies

Hi, I have a question concerning the VHDL description of a bidirectional bus. This bus comes from (goes to) an SRAM which I try to simulate...

Hi, I have a question concerning the VHDL description of a bidirectional bus. This bus comes from (goes to) an SRAM which I try to simulate with a corresponding VHDL model. Now I have an INOUT pin at my SRAM-Controller : Sram_data : inout(7 downto 0); Within my SRAM-Controller I have the local signals l_sram_data_out : std_logic_vector(7 downto 0); l_sram_data_in : std_logic_vect...


how i can use the external SRAM of FPGA

Started by Anonymous in comp.arch.fpga8 years ago 7 replies

i tried a description of RAM but i can't syntesize it and i have the following error: ERROR:Pack:18 - The design is too large for the given...

i tried a description of RAM but i can't syntesize it and i have the following error: ERROR:Pack:18 - The design is too large for the given device and package. i think i will be to use the external SRAM FPGA's board, but i don't know if i can use it without EDK and how i can read and write in this SRAM.


Hve to know the pin connection between cpld and fpga in my design

Started by senthil in comp.arch.fpga13 years ago

Hi Friends, In my board i have SRAM, Spartan-3 FPGA ,CPLD Xc95144xl and PC104 Connector (ISA bus header). I want to pass the data stored in...

Hi Friends, In my board i have SRAM, Spartan-3 FPGA ,CPLD Xc95144xl and PC104 Connector (ISA bus header). I want to pass the data stored in SRAM to PC104 . in between that with the help of spartan-3 only data stored in SRAM. ____ ______ ______ _______ |pc | | | | | | | |104 | | CPLD | |SP-3 | | SRAM |


Displays an image in the XS Board RAM on a VGA monitor

Started by greenplanet in comp.arch.fpga12 years ago 9 replies

Dear all, This may sound stupid to ask, but I am very frustrating now as my deadline is approaching. I want to make use of the VGA...

Dear all, This may sound stupid to ask, but I am very frustrating now as my deadline is approaching. I want to make use of the VGA generator example on www.xess.com. How could I write/read data to the specific address of the SRAM? I would have to have a SRAM controller that writes and reads data to the SRAM? How should that be implemented in VHDL? What else do I need? I am planning t...


async. SRAM control signal generation

Started by whygee in comp.arch.fpga8 years ago 9 replies

Hello, I've been busy lately, trying to understand how to interface asynchronous SRAMs (like IDT 71V016, CY7C10xx or other 16-bit wide and...

Hello, I've been busy lately, trying to understand how to interface asynchronous SRAMs (like IDT 71V016, CY7C10xx or other 16-bit wide and fast parts in TSOP-II) I have found some descriptions of multicycle methods, using FSMs, but this does not fit my target because my circuits already run at "nominal speed" (8 to 15ns cycles, depending on the SRAM chip). So I attempt to find how SRAM re...


Digilent SRAM Controller

Started by al99999 in comp.arch.fpga12 years ago 6 replies

Hi, I was wondering if anybody had designed a vhdl sram controller for the Digilent Memory Expansion board that is designed for the spartan...

Hi, I was wondering if anybody had designed a vhdl sram controller for the Digilent Memory Expansion board that is designed for the spartan 3 starter kit. It is just two ISSI IS61LV5128AL sram chips. I have tried writing a controller but cant seem to get it to work!! Thank a lot, Alastair


Virtex-5 DDRII SRAM Calibration Issues

Started by Colin in comp.arch.fpga8 years ago

Hi guys, I'm trying to use a MIG v2.3 generated DDRII SRAM controller to verify our hardware for a 36 Mb, x18, Burst length 4, GSI SRAM chip....

Hi guys, I'm trying to use a MIG v2.3 generated DDRII SRAM controller to verify our hardware for a 36 Mb, x18, Burst length 4, GSI SRAM chip. We're using a Virtex-5 LX110T chip with a 1738 package size. The design passes stage 1 calibration but hangs during stage 2 calibration. The same behaviour is exhibited when running the controller at 250 MHz or 200 MHz. Both the controller and the SRAM...


Warning appeared while inferring SRAM on xilinx Virtex-E by synplify 7.3.1

Started by boku...@gmail.com in comp.arch.fpga12 years ago

Dear all, While I tried to infer SRAM in synplify7.3. It came out the following warning. Though I see the log and 7.1 did gen the SRAM...

Dear all, While I tried to infer SRAM in synplify7.3. It came out the following warning. Though I see the log and 7.1 did gen the SRAM by Block RAM. I wonder if there's any answer or solution to this warning. Thank you very much!~ @W: Could not implement Block RAM. Is the read address registered using the same clock as the RAM?


NIOS SRAM Problem with Stratix

Started by Anonymous in comp.arch.fpga12 years ago 1 reply

We have a NIOS design running at a clock speed of 92 MHz in a Stratix part that will have Flash and SRAM. All of our program memory is to reside...

We have a NIOS design running at a clock speed of 92 MHz in a Stratix part that will have Flash and SRAM. All of our program memory is to reside in SRAM(IDT714V416L) after boot from flash. We are able to run the debugger on one out of 10 of our boards but the other 9 seem to be having problems just getting started. Almost looks like we are in a permanent reset(reset has been verified to be ...