information about Nuhorizon Spartan-3 Development Board ?

Started by jerome in comp.arch.fpga16 years ago 5 replies

Hello, Could someone give me information about the Nuhorizon Spartan-3 Development Board? It seems to be a good one based upon the Spartan-3...

Hello, Could someone give me information about the Nuhorizon Spartan-3 Development Board? It seems to be a good one based upon the Spartan-3 400 thousand gate FPGA (XC3S400-4PQ208C). Could someone confirme me I can use it with the ISE Webpack 6? A contact in NuHorizon told me I need full software, but I don't understand. Any other comment or suggestion? Thanks, Jerome.


Xilinx Spartan 3 DCM/DFS

Started by Tony C in comp.arch.fpga16 years ago 1 reply

I noticed that for Spartan 3 the DCM status does not define bit 2 any more. In Virtex II it meant that the DFS was stopped. Does this mean the...

I noticed that for Spartan 3 the DCM status does not define bit 2 any more. In Virtex II it meant that the DFS was stopped. Does this mean the DFS never stops? I want to use DFS mode (no CLKFB). How do I know if I need to reset the DCM? Thanks, Tony


Using Spartan XL w/ modern ISE

Started by Vadim Vaynerman in comp.arch.fpga16 years ago 1 reply

Hi all, I am wondering if there is any way to use my legacy Spartan XL devices with ISE/WebPack as the front end. Is there anything I can do,...

Hi all, I am wondering if there is any way to use my legacy Spartan XL devices with ISE/WebPack as the front end. Is there anything I can do, or would I have to fall back to the old ISE Classic/LeonardoSpectrum routine? Thanks, Vadim


Understanding Xilinx Spartan 3 datasheet IOB timing information

Started by Andrew in comp.arch.fpga16 years ago 1 reply

Hi, Im calculating the memory bandwidth achievable when interfacing a Xilinx Spartan 3 (XC3S200, -4 speedgrade) with a Samsung 133MHz ZBT SRAM...

Hi, Im calculating the memory bandwidth achievable when interfacing a Xilinx Spartan 3 (XC3S200, -4 speedgrade) with a Samsung 133MHz ZBT SRAM (128k x 36bit). In general I have found the Spartan 3 datasheet very good (I like the text/description column in the switching characteristics section of the datasheet) but in the following instance I am stuck (probably due to my lack of understanding...


Spartan 3 Kit

Started by Brad Smallridge in comp.arch.fpga16 years ago 4 replies

Where is the demo software for this wonderful Spartan 3 kit? I was most surprised when I plugged in a VGA monitor and saw all the switches,...

Where is the demo software for this wonderful Spartan 3 kit? I was most surprised when I plugged in a VGA monitor and saw all the switches, buttons, and jumper dispalyed in multicolors. Does the keyboard input do something as well?


Spartan 3E availability

Started by Brad in comp.arch.fpga15 years ago 2 replies

Hi all, Have people had reasonable success getting samples of Spartan3E parts? The XS3S100E, for example. I ask this because I got burned by...

Hi all, Have people had reasonable success getting samples of Spartan3E parts? The XS3S100E, for example. I ask this because I got burned by the slow rollout of Spartan XC3S400s. Brad


Why Spartan-3e is the best

Started by Antti Lukats in comp.arch.fpga15 years ago 17 replies

Why Spartan-3e is the best ================== Antti Lukats 4.Nov 2005 (I was asked about why I think so in private, but I think my...

Why Spartan-3e is the best ================== Antti Lukats 4.Nov 2005 (I was asked about why I think so in private, but I think my response could have more general interest so I am posting the reply to c.a.f.) ------------------------------------------------------------- At first look there differences between S3 and S3e may not be so significant however there are several small ...


Interfacing Compact Flash with Spartan 3

Started by George Mercury in comp.arch.fpga15 years ago 3 replies

Hello, In out project, we have to interface a Compact Flash card with a Spartan-3 fpga in Ultra-DMA mode. In the CF 3.0 specifications...

Hello, In out project, we have to interface a Compact Flash card with a Spartan-3 fpga in Ultra-DMA mode. In the CF 3.0 specifications it states, that most of the lines need series termination resistors. We were just wondering, if those termination resistors are really needed, since the CF will be no more than an inch away from the Spartan 3. If they are indeed needed, we might have a proble...


DCM spartan 3 variable frequency divider

Started by Monica in comp.arch.fpga14 years ago 11 replies

Hello all, I am monica from germany.I am using xilinx spartan 3 FPGA.I have a peculiar problem with DCM in spartan 3 FPGA. The input...

Hello all, I am monica from germany.I am using xilinx spartan 3 FPGA.I have a peculiar problem with DCM in spartan 3 FPGA. The input frequency to the FPGA is from another system which gives a frequency arround 40 MHz and the FPGA is supposed to generate 1/8 th of the input frequency,I have implemented it by using DCM.dcmLocked is asserted(dcm locked) and it works fine. On certain cond...


3.3V configuration of Spartan-3?

Started by Evan Lavelle in comp.arch.fpga14 years ago 3 replies

I've got a Spartan-3 which is configured (in master serial mode) from an XCF04S, and which is also in a JTAG chain which looks like...

I've got a Spartan-3 which is configured (in master serial mode) from an XCF04S, and which is also in a JTAG chain which looks like this: connector -> Serial PROM/XCF04S -> XC3S1000 -> 3.3V device -> - connector


Spartan-3 3S50 in Web ISE 5.2i = no block RAM, no multiplier?

Started by Kirill 'Big K' Katsnelson in comp.arch.fpga17 years ago 6 replies

I downloaded Xilinx free Web ISE 5.2i, and toying with different design to get the feeling of this Spartan-3 thingy. The only Spartan-3 device...

I downloaded Xilinx free Web ISE 5.2i, and toying with different design to get the feeling of this Spartan-3 thingy. The only Spartan-3 device supposed to be supported by the free verison is 3S50. I am saying "supposed", because I cannot make it instantiate neither multipliers nor block RAMs. According to the data sheet, there are enough of them in the device, but mapper thinks there are no...


First MicroBlaze demo design for Spartan-3A Starterkit

Started by Antti in comp.arch.fpga13 years ago 8 replies

Hi Xilinx hasnt provided ANY MicroBlaze demos for the new Spartan-3A Starterkit so others have to fill the gap, and I am trying to make...

Hi Xilinx hasnt provided ANY MicroBlaze demos for the new Spartan-3A Starterkit so others have to fill the gap, and I am trying to make a start, here is very simple EDK system that is tested to work on Spartan-3A Starterkit http://www.xilant.com/index.php?option=com_remository&Itemid=36&func=select&id=1 Its rather basic system with UART and GPIO, but it is known to work so can be used...


Using BUFGMUX component in Spartan-3

Started by Paul Bobko in comp.arch.fpga15 years ago

Has anyone had any experience directly implementing BUFGMUX components in a Spartan-3 device. I know this sounds like a very simple task but I...

Has anyone had any experience directly implementing BUFGMUX components in a Spartan-3 device. I know this sounds like a very simple task but I can't seem to get this thing to route. I am simply attempting to select between 2 separate clock signals and route them to a DCM to be deskewed prior to use throughout the device. The part is a Spartan-3 XC3S400-fg456c -4. The 2 clock signals ...


Spartan-3 starter kit strange problem

Started by jmariano in comp.arch.fpga14 years ago 2 replies

Dear All, I'm having a strange problem with my design that is driving me nuts... I'm a newcomer to FPGA in general and to Xilinx tools in...

Dear All, I'm having a strange problem with my design that is driving me nuts... I'm a newcomer to FPGA in general and to Xilinx tools in particular. I'm using a Spartan-3 starter kit board with a XC3S200FT256 FPGA and ISE & EDK 7.1. My idea is to use the board as a controller for my hardware project. I've started with one of EDK's reference designs (Spartan-3 MicroBlaze Example Desig...


Maximum LVDS-rate of Spartan 3E

Started by Thomas Entner in comp.arch.fpga15 years ago

Does anybody know the maximum LVDS-rate of Spartan 3E? I did not find anything in the datasheets, while the Spartan-3 datasheets says 622 Mb/s...

Does anybody know the maximum LVDS-rate of Spartan 3E? I did not find anything in the datasheets, while the Spartan-3 datasheets says 622 Mb/s IO transfer-rate (I think this is valid for LVDS). As we know our friends at X & A, when a nice high number gets quietly removed from the feature-list on the front page of the data-sheet, there is a reason for it... Or was I maybe just blind? ...


C source for Spartan-3 with microblaze soft core for RS-232 comm

Started by Anonymous in comp.arch.fpga15 years ago 1 reply

Has anyone had any luck programming the Spartan-3 Starter board RS-232 using C? I am trying to send/receive/monitor all data going over...

Has anyone had any luck programming the Spartan-3 Starter board RS-232 using C? I am trying to send/receive/monitor all data going over COM1 Thanks


Spartan-3AN

Started by self in comp.arch.fpga13 years ago

Does anyone have any info on the new non-volatile Spartan parts?

Does anyone have any info on the new non-volatile Spartan parts?


Why is Spartan-3 more expensive than Cyclone?

Started by Anonymous in comp.arch.fpga14 years ago 5 replies

Hi everyone, I compared the prices of two FPGAs from Digikey (http://www.digikey.com): +) Xilinx Spartan-3, XC3S1000 - 4FTG256C with LC:1920,...

Hi everyone, I compared the prices of two FPGAs from Digikey (http://www.digikey.com): +) Xilinx Spartan-3, XC3S1000 - 4FTG256C with LC:1920, I/O pins:173. Price: 47.87$ +) Altera Cyclone, EP1C6Q240C8N - ND with LC:5980, I/O pins:185. Price: 18.9$ Im relativly new to the FPGA world, but given the larger numbers of LC's and I/O pins that cyclone has, I don't understand why spartan-3 ...


Xilinx Spartan 3 CLB Slice Options - more detail than in datasheet available?

Started by Andrew FPGA in comp.arch.fpga15 years ago 3 replies

Hi, I am implementing a particular voice compression algorithm in a Spartan 3 FPGA and am directly instantiating Xilinx primatives to get the...

Hi, I am implementing a particular voice compression algorithm in a Spartan 3 FPGA and am directly instantiating Xilinx primatives to get the best (and most reliable) performance, I hope. The spartan 3 datasheet provides a "Figure 6: Simplified Diagram of the Left-Hand SLICEM". This info is good but I'm wanting more detail than is provided in this diagram. The datasheet hints there is more "...


JTAG chaining of two different Xilinx Spartan 3E boards

Started by Anonymous in comp.arch.fpga14 years ago 2 replies

Hi, I've two development boards with me. 1) Spartan 3E Sample Pack(XC3S100E) with a standard 6-pin JTAG connector 2) Spartan 3E Starter...

Hi, I've two development boards with me. 1) Spartan 3E Sample Pack(XC3S100E) with a standard 6-pin JTAG connector 2) Spartan 3E Starter Kit(XC3S500E) with a standard 6-pin JTAG interface and on-board digilent USB-JTAG interface. My question is that if I connect the two 6-pin JTAG connectors together like TDO TDI, TDI TDO,TCK TCK, TMS TMS and GND GND the VCCs are not co