Stratix GX

Started by jon in comp.arch.fpga8 years ago

I have 54 pcs of a Stratix GX EP2SGX90EF1152C3N I over bought on I will let them go for $200 I also have 40 pcs of Stratix GX...

I have 54 pcs of a Stratix GX EP2SGX90EF1152C3N I over bought on I will let them go for $200 I also have 40 pcs of Stratix GX EP2SGX90FF1508C3N Both products are in original factory packaging. I can also supply on terms on approved credit. Thanks, Jon E. Hansen (949)864-7745


CAM, TCAM in Stratix

Started by freechip in comp.arch.fpga11 years ago 10 replies

Hi, I am working on a 10 Gb Ethernet project (deep packet inspection) and need to implement CAM in my FPGA. I am using a Stratix GX and I don't...

Hi, I am working on a 10 Gb Ethernet project (deep packet inspection) and need to implement CAM in my FPGA. I am using a Stratix GX and I don't think I can use CAM (internal or external) in the stratix GX Dev Board. Let me know your thoughts about that. Thanks a lot.


Stratix II vs Virtex 4

Started by Keith Williams in comp.arch.fpga13 years ago 3 replies

Hello everyone, I have a rather high performance design that acts as a high through-put data path with some DSP manipulation on the way...

Hello everyone, I have a rather high performance design that acts as a high through-put data path with some DSP manipulation on the way through. I had been rather certain that I was going to move through to production using Stratix/Stratix II parts. However, the other day I sat down with a distributor who was able to point out some very interesting items for comparisons with the V4 chip...


V4 vs. Stratix-II...

Started by Joseph H Allen in comp.arch.fpga12 years ago 27 replies

I'm upgrading a design, and I'm in the early phases of choosing a vendor. I'm trying to compare parts based on experience I've had in the past,...

I'm upgrading a design, and I'm in the early phases of choosing a vendor. I'm trying to compare parts based on experience I've had in the past, so I'm focusing on block RAM clock to out delay as a critical performance number: Altera M4K vs. Xilinx Block RAM clock to out delay, non-registered outputs: Stratix-II -3 2.46 ns Stratix-II -4 2.828 ns Stratix-II -5 3.393 ns Xilinx-V4 -11 1....


Stratix IV Announced

Started by John Adair in comp.arch.fpga9 years ago 16 replies

Altera have put out a press release announcing Stratix IV. Handbook http://www.altera.com/literature/hb/stratix-iv/stx4_5v4.pdf. Interestingly...

Altera have put out a press release announcing Stratix IV. Handbook http://www.altera.com/literature/hb/stratix-iv/stx4_5v4.pdf. Interestingly it's gone 40nm and does not appear to have a true 3.3V compatability so buy your shares in manufacurers of bus switches now. John Adair Enterpoint Ltd.


NIOS Board Stratix Edition - FPGA won't configure

Started by vadim in comp.arch.fpga13 years ago 6 replies

I am having problem with my NIOS Stratix Board. I am not able to download just my own, simple, compiled VHDL code onto the Stratix FPGA. The...

I am having problem with my NIOS Stratix Board. I am not able to download just my own, simple, compiled VHDL code onto the Stratix FPGA. The device is EP1S10F780C6ES. After JTAG (ByteBlaster) download finishes, the board resets and MAX configuration-device loads Stratix with the default configuration stored in the on-board FLASH memory (which is a NIOS based server thingy). I tried loading ...


Stratix GX

Started by jon in comp.arch.fpga10 years ago 1 reply

Can anyone help on finding a home for the Altera Stratix GX chips. I am in a situation where one of my contracted accounts has purchased the...

Can anyone help on finding a home for the Altera Stratix GX chips. I am in a situation where one of my contracted accounts has purchased the Altera Stratix GX product prematurely. They are not going to be doing the build the product was procured for. Basically they are in a situation where they will let product go significantly below factory direct pricing. Please let me know if you know an...


equivalent Xilinx FPGA for Altera Stratix II GX-60 ,Altera Stratix II GX-90

Started by chai...@gmail.com in comp.arch.fpga10 years ago 3 replies

i need the equivalent Xilinx FPGA for the following altera devices. - Altera Stratix II GX-60 - Altera Stratix II...

i need the equivalent Xilinx FPGA for the following altera devices. - Altera Stratix II GX-60 - Altera Stratix II GX-90 in terms of the resources available in these devices (logic, block ram, dcms, global clock etc) with those available in Xilinx FPGAs. thanks


Altera-Xilinx interfacing SERDES transcievers problem

Started by vasile in comp.arch.fpga10 years ago 3 replies

Hi, Who could enlighten me with the followings: I need to interface a SERDES transciever from a VIRTEX5 FPGA with a STRATIX II IO. Things...

Hi, Who could enlighten me with the followings: I need to interface a SERDES transciever from a VIRTEX5 FPGA with a STRATIX II IO. Things would be easiest if I'll have a Stratix II GX instead of Stratix II, but the GX FPGA has no HARDCOPY II structured Altera ASIC corespondent, so I can't use a GX because of finacial reasons (and huge ball numbers, improper for this design). How could I...


Nios II - Booting software from Flash

Started by Joseph Tan in comp.arch.fpga12 years ago 3 replies

Hi, Has anyone got NIOS software to boot from Flash? I'm working on a Stratix II-based design with onboard NIOS and peripherals (16MB...

Hi, Has anyone got NIOS software to boot from Flash? I'm working on a Stratix II-based design with onboard NIOS and peripherals (16MB flash, Ethernet, SDRAM etc). The Flash, Ethernet, and SDRAM components are wired to the Stratix-II via an Avalon tri-state bus, similar to the design on the Stratix Edition Nios development kit. A single Nios CPU core is running at 50MHz.on the Stratix II....


Stratix II vs. Virtex 4 - features and performance

Started by Dave Greenfield in comp.arch.fpga13 years ago 18 replies

Responding to comments on features and performance . . . Stratix II Features: Altera has led the innovation to introduce...

Responding to comments on features and performance . . . Stratix II Features: Altera has led the innovation to introduce high-density, high-performance FPGAs. In 2002, the Stratix family won EDN Innovation of Year award over Virtex-II Pro. This year, we introduced the Stratix II family which includes a new logic structure, a whole new set of features, and breakthrough performance. Alte...


What happened to the Cyclone IV?

Started by Philipp Klaus Krause in comp.arch.fpga9 years ago 6 replies

According to Altera's 2005 roadmap it was supposed to be available shortly after the Stratix IV and far earlier than Stratix IV GX and Hardcopy...

According to Altera's 2005 roadmap it was supposed to be available shortly after the Stratix IV and far earlier than Stratix IV GX and Hardcopy IV. Philipp


Stratix II

Started by jon in comp.arch.fpga8 years ago

Does anyone have any surplus on any of the Stratix II FPGA. Small or large quantities would help. Thanks, Jon E. Hansen (949)864-7745

Does anyone have any surplus on any of the Stratix II FPGA. Small or large quantities would help. Thanks, Jon E. Hansen (949)864-7745


Interfacing FPGA to on-board SRAM Stratix EP1S40F780C5

Started by Edward in comp.arch.fpga13 years ago 4 replies

Hello All, I am trying to interface the on-board SRAM (IDT71V416 256Kx16) to the FPGA on the Stratix. It is not installed among the library...

Hello All, I am trying to interface the on-board SRAM (IDT71V416 256Kx16) to the FPGA on the Stratix. It is not installed among the library components in the SOPC builder so I cannot instantiate it automatically. I have the datasheet for the SRAM but I need to know where the address, data pins etc. are connected to the FPGA. The pin-out table doesn't seem to specify that in the Stratix h...


Stratix DSP Block: Choosing which FFs are enabled

Started by Rajeev in comp.arch.fpga13 years ago 2 replies

I'm trying to increase the speed of my Stratix design and would like to change which FFs are turned on within a DSP block. The Stratix...

I'm trying to increase the speed of my Stratix design and would like to change which FFs are turned on within a DSP block. The Stratix handbook shows the DSP path something like this: [ FF ] [ X ] [ FF ] [ + ] [ FF ] where [X] is the multiplier block, [+] is an accumulate block and all registers are optional. I don't use any of the accumulators, and I use pipeline_delay=2 going throu...


Stratix II GX Transceivers

Started by jjli...@hotmail.com in comp.arch.fpga11 years ago 3 replies

Hello, I'm looking to do a design involving data rates near 4Gbps and was looking at using Altera's Stratix II GX transceivers to drive the data...

Hello, I'm looking to do a design involving data rates near 4Gbps and was looking at using Altera's Stratix II GX transceivers to drive the data to a 4Gbps single-mode fiber-optic transceiver. I'm interested in how well the Stratix can perform this task, if anyone has some experience using the transceivers could you please let me know how well it worked for you? I've read the Altera's web sit...


Clock problem? Altera Stratix-II ES and MP

Started by Tomoya in comp.arch.fpga12 years ago 2 replies

Hi, all. This is Tomoya greeting from Japan. I would like to hear about Altera Stratix-II ES(engineering sample)/MP(mass production)...

Hi, all. This is Tomoya greeting from Japan. I would like to hear about Altera Stratix-II ES(engineering sample)/MP(mass production) differences. Here is background of our isse (we're facing); We'd made three DDR evaluation boards using Altera Stratix-II EP2S180/130. It has DDR interface, DDR memories, and many IOs (GPIO: General purpose IO). At first, we used EP2S180/130ES (engineer...


altera stratix problem

Started by vlsi_learner in comp.arch.fpga13 years ago 7 replies

I am designing an encryption algorithm using VHDL & targetting it to Stratix EP1S10F780C6.The problem is that post P&R simulation results are...

I am designing an encryption algorithm using VHDL & targetting it to Stratix EP1S10F780C6.The problem is that post P&R simulation results are not correct.however when i target to Stratix EP1S10F780C5, i get the correct encrypted/decrypted output.How does the speed grade affect the post P&R output.The device i m using is the same.only spped grade is diffeterent.I am using Quartus synthesis too...


Timing model for MultiTrack interconnects in Stratix?

Started by Peter Sommerfeld in comp.arch.fpga14 years ago 3 replies

Hi, I am interested in the timing model of the MultiTrack interconnects on Stratix. The timing models for most resources (LEs, M4ks, IOs,...

Hi, I am interested in the timing model of the MultiTrack interconnects on Stratix. The timing models for most resources (LEs, M4ks, IOs, etc) are described in detail in the Stratix handbook, but, curiously, while the symbols are defined for the MultiTracks (R4, R8, R24, C4, C8, C16) in the latest handbook (pg 4-25), the actual timing numbers are never given. Does anyone have this in...


Updated Stratix II Power Specs & Explanation

Started by Paul Leventis in comp.arch.fpga13 years ago 40 replies

Hi, Today we released our updated power specs for Stratix II. Some highlights of the updates found in the Stratix II Early Power...

Hi, Today we released our updated power specs for Stratix II. Some highlights of the updates found in the Stratix II Early Power Estimator V2.1 tool: (1) Reduced static power by up to 47%. We've measured many units from across the product family, and have the data to tighten the spec compared to our previous conservative/estimated values. The amount of change varies from family membe...