Altera Stratix kit PCI to DDR reference design

Started by E. van Putten in comp.arch.fpga15 years ago

Hi everbody, The Stratix PCI kit is a 32/64-bits PCI board from Altera with 256 MB of DDR SDRAM (SO-DIMM). This kit includes a nice reference...

Hi everbody, The Stratix PCI kit is a 32/64-bits PCI board from Altera with 256 MB of DDR SDRAM (SO-DIMM). This kit includes a nice reference design that has a PCI to DDR bridge. We would like to use this design as a starting point for our own designs. Unfortunately this design only works with the old Quartus II v2.1 and the v1.2.1 SDRAM IP Megacore from Altera. Importing the older pr...


High Speed Development Board

Started by freechip in comp.arch.fpga14 years ago 1 reply

Hi, I am working on a 10 Gigabit Ethernet Projet. I have to choose a High-Speed Development Board. I don't know yet which kind of FPGA I am...

Hi, I am working on a 10 Gigabit Ethernet Projet. I have to choose a High-Speed Development Board. I don't know yet which kind of FPGA I am going to use. (Altera or Xilinx). I saw on Altera's Web Site the "Stratix GX High-Speed Development Board" http://www.altera.com/literature/ug/ug_stx_gx_hs_dev_kit.pdf I saw on Altera's Web Site a second High Speed Development: "Stratix II High-Spee...


Stratix pricing

Started by Jerry in comp.arch.fpga16 years ago 2 replies

We got a quote of around $4k for a EP1S80 from Altera. Yes small quantities. Anybody getting them for much less, say sub...

We got a quote of around $4k for a EP1S80 from Altera. Yes small quantities. Anybody getting them for much less, say sub $500? Tks Jerry


Stratix & PLL

Started by Krzysztof Szczepanski in comp.arch.fpga16 years ago 1 reply

Hello, I have a problem with Stratix's PLLs. I want to feed input of Enhanced PLL from Fast PLL and Enhanced PLL form Enhanced PLL. CLK...

Hello, I have a problem with Stratix's PLLs. I want to feed input of Enhanced PLL from Fast PLL and Enhanced PLL form Enhanced PLL. CLK input -> Fast PLL -> Enhanced PLL -> PLL output -> other logic or CLK input -> Enhanced PLL -> Enhanced PLL -> PLL output -> other logic Is this two co


Need to speed up Stratix compiles.

Started by Pete Fraser in comp.arch.fpga16 years ago 36 replies

We're currently running a 3 GHz Pentium with 2 GB memory under Windows 2000. We hope to speed things up by 15-20%, by going to AMD X86-64 and...

We're currently running a 3 GHz Pentium with 2 GB memory under Windows 2000. We hope to speed things up by 15-20%, by going to AMD X86-64 and / or Linux. Has anybody tried this? Any feedback?


Statix II vs. Virtex 4

Started by Tim Michaels in comp.arch.fpga15 years ago 11 replies

Although I have not posted yet to this group, I have an FPGA question. I am doing an evaluation of the Stratix II and the Virtex 4. ...

Although I have not posted yet to this group, I have an FPGA question. I am doing an evaluation of the Stratix II and the Virtex 4. Does anyone have any comparisons or experience of the features, performance, etc. of the two devices? I am trying to understand the tradeoffs of the two different platforms.


Stratix II - Cyclone II GATE COUNT

Started by Anonymous in comp.arch.fpga12 years ago 2 replies

Hi, Is there an Altera application to count the number of equivalent gates for Logic Elements, Memory, DSP blocks, PLL etc......

Hi, Is there an Altera application to count the number of equivalent gates for Logic Elements, Memory, DSP blocks, PLL etc... ? Thanks... I don't find this information..


uart / Nios2

Started by HB in comp.arch.fpga14 years ago 3 replies

Hi, I 'm trying to use UART with NIOS2 (Stratix). I would like to send a message to Hyperterminal. (not with JTAG_UART, and not with NIOS IDE...

Hi, I 'm trying to use UART with NIOS2 (Stratix). I would like to send a message to Hyperterminal. (not with JTAG_UART, and not with NIOS IDE console) Could you help me ?. (free example could be perfect !). Regards, BH.


OpenSPARC T1 or T2 on Altera EP2S60 or EP2S90

Started by Dennis Yurichev in comp.arch.fpga10 years ago 2 replies

Hi. Does anybody had any real success on running OpenSPARC core on Altera Stratix II?

Hi. Does anybody had any real success on running OpenSPARC core on Altera Stratix II?


Clock J4

Started by Anonymous in comp.arch.fpga14 years ago 1 reply

Dear, I have a question regarding the "SMA connector J4" available on the Nios Development board, Stratix Edition. Can we use it only for...

Dear, I have a question regarding the "SMA connector J4" available on the Nios Development board, Stratix Edition. Can we use it only for an external clock? would it be possible to read any input signal from it, I have an idea how to get the clock so this is not an issue. Thanks in advance, John.


Xilinx/Altera gate equivalence

Started by dudesinmexico in comp.arch.fpga11 years ago 12 replies

Are there any rules of thumb to figure out the equivalent number of logic resources needed to implement the same design on Stratix IV vs.,...

Are there any rules of thumb to figure out the equivalent number of logic resources needed to implement the same design on Stratix IV vs., say, Virtex-4/5? I am thinking of random logic, i.e. a CLB vs. LAB conversion factor... Thanks!


FFT Ccre

Started by Nagaraj in comp.arch.fpga10 years ago

Hi, Where can I get the information on resource usage (and current consumption) of the FFT cores for Altera devices (specifically 32k to 512k...

Hi, Where can I get the information on resource usage (and current consumption) of the FFT cores for Altera devices (specifically 32k to 512k fixed point for Stratix family). I tried a web search but no decent results. Nagaraj


use of JTAG pins

Started by teo_80 in comp.arch.fpga15 years ago 1 reply

Can I use JTAG pins as a user I/O on an Altera Stratix Device ? Matteo

Can I use JTAG pins as a user I/O on an Altera Stratix Device ? Matteo


Stratix-III announced

Started by Antti in comp.arch.fpga13 years ago 8 replies

S-III L == V5LX S-III E == V5SX S-III GX == V5xxT 1000-unit pricing starts at $549 for the EP3SL150 Quartus WebPack support for S-III to be...

S-III L == V5LX S-III E == V5SX S-III GX == V5xxT 1000-unit pricing starts at $549 for the EP3SL150 Quartus WebPack support for S-III to be available on 4 DEC 2006 Antti


Re: Stratix-III announced

Started by unkn...@aol.com in comp.arch.fpga13 years ago 10 replies

Personnaly, I'm also waiting for Cyclone III. Looks promising. By the way, I've been told that MAX III is also on the way ... and that NIOS II...

Personnaly, I'm also waiting for Cyclone III. Looks promising. By the way, I've been told that MAX III is also on the way ... and that NIOS II will be supported :o) ---------------------------------------------- Posted with NewsLeecher v3.5 Beta 5 * http://www.newsleecher.com/?usenet


Need help: Altera ALTPLL_RECONFIG state machine construction

Started by Bob in comp.arch.fpga12 years ago 1 reply

I've asked for help once before on this topic and was directed to look at Ap Note #367. Unfortunately, when I unzip the example designs, I...

I've asked for help once before on this topic and was directed to look at Ap Note #367. Unfortunately, when I unzip the example designs, I didn't find a walk-through or readme file that describes how to go through each example (am I missing something?). I am using a Stratix II part and need to be able to monitor a input pin, after power-up/ reconfiguration is complete, to switch between ...


Switching clocks in Xilinx / Altera devices

Started by ALuPin in comp.arch.fpga15 years ago

Hi out there, I have read an article about a clock multiplexer BUFGMUX which is involved in the VIRTEX II devices. Did somebody have any...

Hi out there, I have read an article about a clock multiplexer BUFGMUX which is involved in the VIRTEX II devices. Did somebody have any experience with that mux ? Is there something comparable in Altera Stratix/Cyclone devices ? I would appreciate any info. Thank you.


nios II stratix II handling interrrupts from uController

Started by badari in comp.arch.fpga14 years ago 2 replies

hi all! I'm using NiosII with StratixII. i wanted to get interrupts from a micro controller of 7.393MHz Oscillator which generates half...

hi all! I'm using NiosII with StratixII. i wanted to get interrupts from a micro controller of 7.393MHz Oscillator which generates half the oscillator clock. Nios works at 50Mhz. so what modification i need to do on nios


Re: Stratix 2 ALUT architecture patented ?

Started by Mikeandmax in comp.arch.fpga16 years ago

Peter writes > But regarding the graves that Austin referred to, they are from: > .............. AMD, Lucent,.......... Quote from Mark...

Peter writes > But regarding the graves that Austin referred to, they are from: > .............. AMD, Lucent,.......... Quote from Mark Twain follows: "Rumors of my untimely demise have been greatly exaggerated." might not be exact, but you get what I mean. This is a terrific newsgroup. I know I have learned a fair amount about the topic while perusing the posts. But let's reme


Gate Count vs Logic Element (LE)

Started by Jasmine Hau in comp.arch.fpga15 years ago 4 replies

Hi, can anybody tell me how to get the total gate count approximation from Logic Elements (LEs) in Altera Stratix and APEX device??? Thank you...

Hi, can anybody tell me how to get the total gate count approximation from Logic Elements (LEs) in Altera Stratix and APEX device??? Thank you very much.