Win an Altera DE0-Nano (Cyclone IV Dev Kit)!

Started by allen in comp.arch.fpga6 years ago 4 replies

Hey guys! Terasic Technologies is holding a contest to WIN the newly released Altera DE0-Nano! Head over to...

Hey guys! Terasic Technologies is holding a contest to WIN the newly released Altera DE0-Nano! Head over to http://www.terasic.com.tw/events/DE0_Nano_Contest/ to leave a comment and win one today!!! Thanks, Allen Houng Terasic Technologies www.terasic.com


Need Terasic LTM Module

Started by Abby in comp.arch.fpga5 years ago

Hi, I delayed too long in ordering a Terasic LTM touchscreen module and now they are listed as phased out with no substitute shown. Anyone...

Hi, I delayed too long in ordering a Terasic LTM touchscreen module and now they are listed as phased out with no substitute shown. Anyone know where I can get one? Or equivalent? Thanks, Gary


Terasic DE1 board commentary

Started by H. Peter Anvin in comp.arch.fpga9 years ago 6 replies

Hello, I am in the process of porting a project of mine from the Cyclone Nios Development Kit to the Terasic DE1 board. The main reason for...

Hello, I am in the process of porting a project of mine from the Cyclone Nios Development Kit to the Terasic DE1 board. The main reason for this is to be able to run on less expensive hardware and thus make the project available to more people (hence "get a better board" is not really an easy answer.) My interest is mostly in computing projects, so my views are certainly biased in that d...


Touchscreen For Terasic Technologies DE0 Nano

Started by Snowy in comp.arch.fpga6 years ago 1 reply

Hi, I am looking for a touchscreen for an DE0 Nano. Terasic's LTM touchscreen is supposed to work but the LTM manual does not mention it. ...

Hi, I am looking for a touchscreen for an DE0 Nano. Terasic's LTM touchscreen is supposed to work but the LTM manual does not mention it. Are there others? A seven inch screen is preferred. Thanks, Gary


Terasic DE1 - expansion port power ratings

Started by Philip Pemberton in comp.arch.fpga9 years ago 1 reply

Hi, I'm currently playing with a Terasic DE1 (aka Altera Cyclone II Starter Board), and looking to attach a little external hardware....

Hi, I'm currently playing with a Terasic DE1 (aka Altera Cyclone II Starter Board), and looking to attach a little external hardware. Specifically, a PIC microcontroller, 40MHz clock oscillator and a couple of TTL buffers. In all likelihood, an external 5V supply will be running the TTL; the PIC and oscillator will (ideally) be powered by the DE1. Both expansion ports provide +5V and +...


Altera HSMC connector

Started by Rick C. Hodgin in comp.arch.fpga1 year ago 18 replies

Hello all. I'm looking for some information about Altera's FPGA. I have this Cyclone V GX dev board: ...

Hello all. I'm looking for some information about Altera's FPGA. I have this Cyclone V GX dev board: https://www.altera.com/products/boards_and_kits/dev-kits/partners/kit-terasic-cyclone-v-gx-start er.html It has a 160-pin HSMC connector, which connects using this flexible cable: https://www.altera.com/en_US/pdfs/literature/ds/hsmc_spec.pdf http://www.terasic.com.tw/cgi-bin


CPC TREX 24MHz Turbo Core available PLUS complete source code

Started by Prodatron / SymbiosiS in comp.arch.fpga11 years ago

Hi, today TobiFlex released his new turbo core for the CPC TREX. http://www.symbos.de/trex.htm The CPC TREX is a complete FPGA-based...

Hi, today TobiFlex released his new turbo core for the CPC TREX. http://www.symbos.de/trex.htm The CPC TREX is a complete FPGA-based implementation of the classic computer Amstrad CPC on a Terasic T-REX C1 board ( http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=39&No=14&Revision= 018&PartNo=1 ). The great thing is, that TobiFlex also released the complete sourc


Is it possible to use a remote desktop viewer on NIOS Linux

Started by Ahmed Abdelfattah in comp.arch.fpga6 years ago

Hello , I am having a project where I need to take control of a pc or a smart phone which has a VNC server using FPGA so I need to run a client...

Hello , I am having a project where I need to take control of a pc or a smart phone which has a VNC server using FPGA so I need to run a client from the FPGA side . Is this possible ? My kit is the terasic de2-115 .It has USB controller chip and Ethernet connections .


Low cost altera board

Started by Alex Gibson in comp.arch.fpga12 years ago 3 replies

Came across this http://www.terasic.com/english/fpga_01.htm Just wondering if anyone has one or has tried one? Designed for multimedia. ...

Came across this http://www.terasic.com/english/fpga_01.htm Just wondering if anyone has one or has tried one? Designed for multimedia. EP1C6Q248C8 vga , tvout , audio out(line out) , ps2 , rs232 , usb programming cf card , config prom , 16 bit audio , 1MB flash + 8MB ram. Looks quite good for US$149 Alex


A few LatticeMico32 questions

Started by Philip Pemberton in comp.arch.fpga7 years ago 4 replies

Hi, It would seem the Lattice Mico32 support forum has gone dead (no posts/ replies since early February), so I'm asking this here in the hope...

Hi, It would seem the Lattice Mico32 support forum has gone dead (no posts/ replies since early February), so I'm asking this here in the hope there's an lm32 guru somewhere out there... I've (successfully) ported the LatticeMico32 CPU core to the Altera Cyclone II (terASIC DE1 platform, aka Cyclone II FPGA Starter Board). Caching seems to work, as do the WISHBONE interfaces (both of th...


How to program altera on power up? or Can't recognize silicon ID for device 1

Started by Guy_FPGA in comp.arch.fpga9 years ago 2 replies

Hello all, I've just finish my design. It is a simple hardware only, no NIOS inside. Now I would like to make it automatically "uploaded" to...

Hello all, I've just finish my design. It is a simple hardware only, no NIOS inside. Now I would like to make it automatically "uploaded" to the fpga on board's power up. I am using Terasic DE3. I read that I need to convert the sof file to jic and the program the EPCS flash... Is it true? I've tried to do so but... it doesn't work I get an error - Info: Configuration succeeded -- 1 d...


Clocking Sync Burst SRAM

Started by Tommy Thorn in comp.arch.fpga9 years ago 9 replies

I wrote a little controller + tester app for the SSRAM on Terasic's DE2-70 which is rated for 200 MHz. I have gotten it working @ 170 MHz, but...

I wrote a little controller + tester app for the SSRAM on Terasic's DE2-70 which is rated for 200 MHz. I have gotten it working @ 170 MHz, but I'm a little uneasy about the SSRAM clock. Being a non-EE I suspect I'm missing something fundamental here. First, all output are fully registered (and constrained to guarantee they stay registered). The main logic is clocked by a PLL. A second but ...


Cheap Ethernet PHY boards?

Started by radarman in comp.arch.fpga8 years ago 4 replies

I have a couple of Altera dev boards - a Terasic DE2, and an old Stratix "SmartPack"; and I really want to play with an Ethernet MAC core. The...

I have a couple of Altera dev boards - a Terasic DE2, and an old Stratix "SmartPack"; and I really want to play with an Ethernet MAC core. The trouble is, the DE2 has a full-blown Ethernet controller - and the SmartPack has nothing. I'm essentially looking for a board that has MII/GMII on one side, and an RJ-45 connector on the other. These exist, but cost hundreds of dollars. (the EVB-LAN...


QuartusII Ver11.0 programmer problems?

Started by Nial Stewart in comp.arch.fpga6 years ago 2 replies

I have a client who is trying to use the QuartusII Ver 11.0 stand alone programmer to program a Cyclone IV board, and is having problems and his...

I have a client who is trying to use the QuartusII Ver 11.0 stand alone programmer to program a Cyclone IV board, and is having problems and his machine isn't seeing the programmer (It's an Entner EEBlaster but it also can't see a Terasic blaster so I'm confident that isn't the problem). Version 9.0 of the programmer can see it OK but can't drive the Cyclone IV on his board. Has anyone ...


Help on TRB_DC2 Camera module interface

Started by sriman in comp.arch.fpga10 years ago 3 replies

I am tring to design a video acquisition system. I am usimg the DE1 borad and the compactable TRB_DC2 camera module with...

I am tring to design a video acquisition system. I am usimg the DE1 borad and the compactable TRB_DC2 camera module with it.(http:// www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=39&No=50). The problem i am facing is on the data sheet 20 pins are assigned to each sensor. i am a newibe to vlsi design. i am unable to distinguish the usage of al the pins. only understood...


Help on TRB_DC2 Camera module interface

Started by sriman in comp.arch.fpga10 years ago

I am tring to design a video acquisition system. I am usimg the DE1 borad and the compactable TRB_DC2 camera module with...

I am tring to design a video acquisition system. I am usimg the DE1 borad and the compactable TRB_DC2 camera module with it.(http:// www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=39&No=50). The problem i am facing is on the data sheet 20 pins are assigned to each sensor. i am a newibe to vlsi design. i am unable to distinguish the usage of al the pins. only understood...


NIOS is stuck at alt_tick after reset

Started by Guy_FPGA in comp.arch.fpga9 years ago 3 replies

Hello all, I am working with Alter NIOS terasic DE3 board- I've written a software for NIOS. When I run it in debug mode it look fine....

Hello all, I am working with Alter NIOS terasic DE3 board- I've written a software for NIOS. When I run it in debug mode it look fine. When I press the on-board reset I can see in the IDE that it has entered reset mode. when I press the resume button - the SW is stuck. If I press the pause I see that the SW is stuck in a loop insited alt_tick.c --> void alt_tick(void)... Does anyone