more and more and more issues with Xilinx tools

Started by Antti Lukats in comp.arch.fpga12 years ago 11 replies

Hi all, FPGA are fun to work with ... when the tools work. New versions of the tools come out, then serice packs, but there is no light that...

Hi all, FPGA are fun to work with ... when the tools work. New versions of the tools come out, then serice packs, but there is no light that the tools would actually work better. This is towards Xilinx tools. I used lately also Quartus 4.2 for several desings and dont recall having any tool related issues at all. http://wiki.openchip.org/index.php/ISE there are some my current identif...


Tools Tree

Started by Nagaraj in comp.arch.fpga14 years ago 6 replies

Hi all, As there are number of point tools available in the industry for FPGA based design and implementation, it is becoming more difficult...

Hi all, As there are number of point tools available in the industry for FPGA based design and implementation, it is becoming more difficult to stick to one flow. Does anybody have some sort of tools tree (2-3 tools against each node in the design flow diagram) available in the industry? This should be independent of any tool vendor but include widely used tools. I mean, I want something ...


Quick question

Started by Jason Berringer in comp.arch.fpga13 years ago 6 replies

Hello all, I'm curious to know the benefits of using third party synthesis tools. For example how much better are synthesis tools like...

Hello all, I'm curious to know the benefits of using third party synthesis tools. For example how much better are synthesis tools like Synplicity or Synplify, etc over just using the vendor tools ISE Webpack. Do you only experience some significant gains with large designs or does it not really matter. I've been using the Xilins synthesis tools for quite a while and have never had a proble...


User Constraint Files

Started by rickman in comp.arch.fpga7 years ago 1 reply

Someone in a meetup group discussion is suggesting that there is a level of interoperability between different brands of tools for the User...

Someone in a meetup group discussion is suggesting that there is a level of interoperability between different brands of tools for the User Constraint File (UCF). I guess I never thought about it and just assumed they would be proprietary. The Lattice tools are based on the same NeoCAD tools the Xilinx tools ar ebased on, so I am not surprised by some degree of commonality. But are Altera ...


independent reviews of EDA tools?

Started by MikeD in comp.arch.fpga11 years ago

Does anyone know of any reviews of different tools, or have any experiance with any of the 3rd party tools, good or bad? For work, I'm looking...

Does anyone know of any reviews of different tools, or have any experiance with any of the 3rd party tools, good or bad? For work, I'm looking into what we need, and what our options are. Right now we just have the basic Altera Quartus II and Nios II tools, and we ordered the full version of Quartus II with Alteras stripped down version of ModelSim. I'm the only guy with a lot of FPGA ex...


how to start with development of eda tools

Started by kevin in comp.arch.fpga13 years ago 11 replies

how to start with development of eda tools(e.g simulation tools and synthesizing tools): what knowledge should i know and where i can...

how to start with development of eda tools(e.g simulation tools and synthesizing tools): what knowledge should i know and where i can find the informations(tutorial, guides or something else) thanks! br


new PC specs for Xilinx tools

Started by Tom Kotwal in comp.arch.fpga8 years ago 14 replies

Hi All, I'm speccing out a new windows PC that I'll use with Xilinx tools, probably Webpack and Modelsim, and I'm looking for some advice to...

Hi All, I'm speccing out a new windows PC that I'll use with Xilinx tools, probably Webpack and Modelsim, and I'm looking for some advice to make sure the tools will run fast. I know memory is important, but what else? Also, what pitfalls should I watch out for? I'm not sure how relevant this info is, but I'm probably going to target something in the ballpark of a Virtex-5 LX50. Also, I'...


open source FPGA tools

Started by Sasa Bremec in comp.arch.fpga13 years ago 1 reply

Hi! I have a question related on design flow and use of open source tools like "icarus verilog". How many of designers out there use this...

Hi! I have a question related on design flow and use of open source tools like "icarus verilog". How many of designers out there use this tools and why? thanks, Sasa


Can't get Actel tools to run on SL4.4 (RHEL 4.4)

Started by General Schvantzkoph in comp.arch.fpga10 years ago

Has anyone been able to get the Actel Linux tools to run? I wasn't able to install them on CentOS5 so booted into Scientific Linux 4.4 (a RHEL...

Has anyone been able to get the Actel Linux tools to run? I wasn't able to install them on CentOS5 so booted into Scientific Linux 4.4 (a RHEL 4.4 clone). Installation went fine in 4.4 but I haven't been able to run the tools. I'm getting, /usr/local/tools/Actel/LiberoLU80_Lin/Libero/bin/windu_scm: relocation error: /usr/local/tools/Actel/LiberoLU80_Lin/Libero/lib/libwinsock50.so: sym...


synthesis tools

Started by axr0284 in comp.arch.fpga10 years ago 8 replies

Hi everybody, I would like to obtain people's opinion on the use of different synthesis tools to target FPGA designs. I am thinking of tools...

Hi everybody, I would like to obtain people's opinion on the use of different synthesis tools to target FPGA designs. I am thinking of tools from Synopsys, Mentor graphics and synplicity. If there are others, I would like to know. These are excellent for targetting ASIC designs where every little space and power dissipation is critical. My question is, is it worth using these expensive tool...


ISE tools to use SMP?

Started by praetorian in comp.arch.fpga12 years ago 1 reply

Does anybody know if ISE tools (bitgen, par, map, etc.) could utilize dual-core CPU's to speed up their process? I am using a P4EE 3GHz on an...

Does anybody know if ISE tools (bitgen, par, map, etc.) could utilize dual-core CPU's to speed up their process? I am using a P4EE 3GHz on an SMP-enabled Linux system. The tools are reported to use only 50% of the CPU time.


Running Xilinx and Altera Tools on Fedora Core 5

Started by Josh Rosen in comp.arch.fpga11 years ago 2 replies

Both Xilinx and Altera make the assumption that their tools are being run on a ridiculously obsolete versions of Linux. The Quartus tools test...

Both Xilinx and Altera make the assumption that their tools are being run on a ridiculously obsolete versions of Linux. The Quartus tools test to see if they are running on Redhat 8, if not they set the LD_ASSUME_KERNEL to 2.4. At one point the Xilinx tools had a requirement that you set the LD_ASSUME_KERNEL to 2.4.7. This didn't cause any problems in earlier version of Fedora Core but it doe...


How good are Actel tools

Started by rickman in comp.arch.fpga8 years ago 7 replies

I know Antti has a lot of experience with Actel, so I expect to hear from him, but I am sure there are others out there with experience of Actel...

I know Antti has a lot of experience with Actel, so I expect to hear from him, but I am sure there are others out there with experience of Actel tools. A customer of mine has told me that he used Actel for a project some 4 or 5 years ago and had a problem with the tools that Actel could not give a fix for. I don't recall how he worked around it and I am sure that particular issue has been f...


comparison of FPGA tools?

Started by Morten Leikvoll in comp.arch.fpga14 years ago

I am looking for new tools for FPGA development and wonder if someone has a comparison of different tools available (everything needed from...

I am looking for new tools for FPGA development and wonder if someone has a comparison of different tools available (everything needed from source to bit configuration code) I like to combine schematics for rough block diagrams and macros for more schematics, VHDL and/or 'C' based language synthesis. I have mainly used the old Xilinx Foundation package (It is still OK but not longer supporte...


Free tools

Started by Roger in comp.arch.fpga13 years ago 2 replies

It's a while since I looked at free tools but when I did, Altera's Web version of Quartus was a great deal. I've checked back and it appears...

It's a while since I looked at free tools but when I did, Altera's Web version of Quartus was a great deal. I've checked back and it appears that the Web version is time limited now, is this correct? If so, does anyone know of any free tools from the main FPGA manufacturers? TIA. Rog.


ISE tools not detecting IOSTANDARD conflicts within bank

Started by Eli in comp.arch.fpga7 years ago 4 replies

Hello, I'm running ISE 9.2.03i on a design for Spartan 3E (3s250e-4tq144). For whoever wishes to skip the long description below, the idea...

Hello, I'm running ISE 9.2.03i on a design for Spartan 3E (3s250e-4tq144). For whoever wishes to skip the long description below, the idea is simple: The tools should not agree to place pins with conflicting IO standards, such as LVTTL and LVCMOS25, on the same bank. And suddenly I caught the tools not noticing this. This clearly looks like a bug, among others because slight tweaks with ...


QUES: Where can I find Xilinx M1 tools

Started by Ted in comp.arch.fpga14 years ago 6 replies

I have to make a change to a XC4005pc84-5 part but I don't have the tools that support XC4000 parts. I've gone all the way back to Alliance...

I have to make a change to a XC4005pc84-5 part but I don't have the tools that support XC4000 parts. I've gone all the way back to Alliance Series 1.5i and XC4000E's are supported but not XC4000's. I believe I need an old set of M1 tools but I don't know where to find them. Does anyone know where I can get an old set of Xilinx tools that can supports XC4000 parts (not XC4000E parts). Th...


programming devices using other tools

Started by antonio bergnoli in comp.arch.fpga12 years ago 3 replies

Hi, I want to know if anybody has never programmed fpga or proms not using Impact or Quartus programmer but other (third party) tools. If yes,...

Hi, I want to know if anybody has never programmed fpga or proms not using Impact or Quartus programmer but other (third party) tools. If yes, how ? which are the file formats to use? Thanks in advance.


Open source access to generate netlists into Altera tools? Others?

Started by Anonymous in comp.arch.fpga12 years ago 3 replies

Ok, to be completely fair now that Xilinx clearly doesn't allow open source tools to generate net lists for the features of current...

Ok, to be completely fair now that Xilinx clearly doesn't allow open source tools to generate net lists for the features of current Xilinx devices (other than old limited EDIF and XNF interfaces), just what access does open source have to generate usable netlists for Altera products? What fpga companies are open to open source tools augmenting their vendor supplied tools to support their p...


Re: XML for LUT+FF netlist representation in (academic) tools

Started by Andreas Ehliar in comp.arch.fpga8 years ago 2 replies

On 2009-05-14, acd wrote: > I think this second step should be easily doable with XSLT if the > netlist is represented as XML. > I wonder...

On 2009-05-14, acd wrote: > I think this second step should be easily doable with XSLT if the > netlist is represented as XML. > I wonder if there are existing formats and tools to do this. I would look at the kind of formats that commercial synthesis tools output. This is most likely going to be some sort of EDIF based format. I know that Precision outputs EDIF files