Microblaze interrupt problem

Started by Anonymous in comp.arch.fpga12 years ago

hello, I have a microblaze system with a uart and a timer (both produce interrupt).The interrupts are handled by intc.Uart interrupt is...

hello, I have a microblaze system with a uart and a timer (both produce interrupt).The interrupts are handled by intc.Uart interrupt is the highest priority followed by timer interrupt. 1. can microblaze read only the required data from the uart at a time.like say i want to get a frame from uart i.e data from one flag to another flag and then stop reading the bytes fro uart.When i tried ...


RS232, UART & Igloo nano Kit

Started by Bert_Paris in comp.arch.fpga8 years ago

Hello, I have built an Application Note for newbies (& students !) who want to understand and implement RS232 (UART) in an FPGA. Especially...

Hello, I have built an Application Note for newbies (& students !) who want to understand and implement RS232 (UART) in an FPGA. Especially when it's an assignement, they should follow this document instead of asking for the UART code (which I give away only in the context of larger educational projects). I have also built a nice (I think) Tutorial to implement and test a simple UART i...


EDK OPB Uart 16550

Started by MS in comp.arch.fpga13 years ago 3 replies

We are using the trial version of the OPB Uart 16550 in one of our designs. We are running this at 19200,8,N,1, no flow control. We are using...

We are using the trial version of the OPB Uart 16550 in one of our designs. We are running this at 19200,8,N,1, no flow control. We are using Hyperterminal- and we are able to access the UART ok for generic stuff. Print/scan. We then run a test where we send a bunch of checksum frames (Srecords) to the UART and check them on the PPC. This is done via Hyperterm- send text file. The pro...


Help needed!!interrupt handling in microblaze system

Started by Anonymous in comp.arch.fpga12 years ago 1 reply

hello, I have a microblaze system with a uart and a timer (both produce interrupt).The interrupts are handled by intc.Uart interrupt is...

hello, I have a microblaze system with a uart and a timer (both produce interrupt).The interrupts are handled by intc.Uart interrupt is the highest priority followed by timer interrupt. 1. can microblaze read only the required data from the uart at a time.like say i want to get a frame from uart i.e data from one flag to another flag and then stop reading the bytes fro uart.When i tr...


JTAG as UART for PowerPC in XMD.

Started by Pablo in comp.arch.fpga10 years ago 4 replies

Hi, I have seen about configuring the JTAG as UART since I have not RS232 port in my board. I have found that Xilinx provides OPB_MDM as uart...

Hi, I have seen about configuring the JTAG as UART since I have not RS232 port in my board. I have found that Xilinx provides OPB_MDM as uart with C_USE_UART PARAMETER, but in my desing I use PowerPC. In powerPC the debug is done by jtag_cntlr and not by opb_mdm so console says that "opb_mdm_0 is not accessible from processor ppc405_0". Has anyone configured JTAG as UART in PowerPC? Rega...


test UART

Started by ZHI in comp.arch.fpga10 years ago

Hi, All I want to use UART to do the transmission between Matlab and FPGA board. I found one from others. I made a simple test to...

Hi, All I want to use UART to do the transmission between Matlab and FPGA board. I found one from others. I made a simple test to realize transmit data to uart and transmit back to matlab. I will write some parts codes of my test here to make sure you know what I am doing. entity uart-top is port( sys_clock : in std_logic; PB_LEFT : in std_logic; RS232_RTS_IN : IN std_logic; ...


Problem with UART EDK 9.2.02i

Started by Anonymous in comp.arch.fpga9 years ago 4 replies

Helo! I'm using a newest ver. of ISE and EDK (with all SP) on Linux Ubuntu (last relese), and I expirience a problem with UART. I've created...

Helo! I'm using a newest ver. of ISE and EDK (with all SP) on Linux Ubuntu (last relese), and I expirience a problem with UART. I've created two identical basic projects, one using 9.1 (on Windows) and the other using 9.2. (on Linux). Projects contains MB processor with UART lite only (uart is set as stdin/out), and TestApp_Memory generated application. The project created on Win (EDK 9.1) ...


UART master core

Started by Anonymous in comp.arch.fpga9 years ago 1 reply

Hello, I have 2 boards, of which one has PPC core and other do not. [board1 /w PPC]-------uart-------[board2 /wo PPC] I want to use UART...

Hello, I have 2 boards, of which one has PPC core and other do not. [board1 /w PPC]-------uart-------[board2 /wo PPC] I want to use UART as a debug interface for board2. So,I am looking for a UART Master core that shall be Maser on the PLB/ OPB bus that I can use it in board2 FPGA. The Xilinx EDK library provide UART cores that has PLB/OPB interfaces as core side interfaces. But t...


Large SKEW kill UART?

Started by Anonymous in comp.arch.fpga13 years ago 1 reply

Hi, all: Implementing a UART(asic core) into XILINX Virtex2 3000-5. Due to 99% slices is used (2 slices is unused), the skew of the gated clock...

Hi, all: Implementing a UART(asic core) into XILINX Virtex2 3000-5. Due to 99% slices is used (2 slices is unused), the skew of the gated clock in UART is a little large (2-3 ns). On debuging, the UART is work well on some boards, however, occur error on other boards. And when I add a skew constraint to limit the skew below 1ns, all boards is ok. I hope to know, does par tools do setup / ...


How to direct download to SRAM on Xilinx Spartan3?

Started by Riccardo Fregonese in comp.arch.fpga13 years ago 1 reply

Thanx!!!!! I'm trying to understand something about UART, I've downloaded some IP cores, some app notes... But if I'll add to my design a...

Thanx!!!!! I'm trying to understand something about UART, I've downloaded some IP cores, some app notes... But if I'll add to my design a very simple UART, with a little controller, how can i communicate with that? I downloaded the core UART from www.opencores.org, can I read/load data from/to it with Windows Hyperterminal (I have win2000)? And how? Here's the miniUART entity enti...


NIOS: plugs without an uart?

Started by Petter Gustad in comp.arch.fpga14 years ago

Is it possible to use the plugs library without an uart? I keep getting: cpu_sdk/lib/libnios32.a(plugs_print.c.o): In function...

Is it possible to use the plugs library without an uart? I keep getting: cpu_sdk/lib/libnios32.a(plugs_print.c.o): In function `d_print_tcp_packet': plugs_print.c.o(.text+0x384): undefined reference to `nr_uart_txchar' ... I would expect no calls to any uart routines whenever I build a system with no serial ports. I've NOT included the plugs debugging routines. However, I have i...


UART testbench debug

Started by uche in comp.arch.fpga8 years ago 2 replies

I am using the following code to test the Ken Chapman's UART. When I run the following code and see the FIFO data at the 'command' output, I do...

I am using the following code to test the Ken Chapman's UART. When I run the following code and see the FIFO data at the 'command' output, I do not get 'A' as intended by the design. Instead, I get some other bit patterns that doesn't make sense. Can anyone see what I am doing wrong with the testbench. Also, I am assuming that I do not need to tamper with the underlying Ken Chapman UART! ...


Smallest GPL UART

Started by Giuseppe Marullo in comp.arch.fpga5 years ago 28 replies

Hi all, I am searching for the smallest/simpler UART in verilog. I need to release the project under GPL and still confused about what are my...

Hi all, I am searching for the smallest/simpler UART in verilog. I need to release the project under GPL and still confused about what are my options. I would go with micro UART by Jeung Joon Lee but I am unable to determine its license. There are others, like osvudu by Timothy Goddard seems released under (a) MIT license, thus compatible with GPL. I need very simple stuff: baud...


Xilinx UART Macro ERROR???

Started by john orlando in comp.arch.fpga14 years ago 5 replies

Hello, We have recently been using the free Xilinx UART macro with the 16-byte FIFO (from app note XAPP223) in a design, instantiated in...

Hello, We have recently been using the free Xilinx UART macro with the 16-byte FIFO (from app note XAPP223) in a design, instantiated in a Virtex XC2V1000. We are using both the Rx and Tx macros (actually, 32 of each for a total of 32 UARTs in the device). Our actual setup looks like this: StrongArm SA-1100 Virtex XC2V1000 32 serial devices where the UART FIFOs in the XC2V1


2 Modules working independently but not together on FPGA

Started by Anonymous in comp.arch.fpga8 years ago 1 reply

Hi, I have 2 modules ( 1 UART and another module used to test external SRAMs ). Every single module is working prefectly when alone on the...

Hi, I have 2 modules ( 1 UART and another module used to test external SRAMs ). Every single module is working prefectly when alone on the Spartan 3 borad. when i put them together, the UART doesn't work anymore. i have the clock excessive skew problem, and i'm pretty sure it comes from there. The RX module is working perfectly while the TX module is not working. the UART provides ...


Issues on Shift Register in a Clockless UART

Started by Shashi in comp.arch.fpga13 years ago 11 replies

Hi, I'm doing a project in clockless uart..as u know that the primary function of uart is parallel to serial conversion while transmitting and...

Hi, I'm doing a project in clockless uart..as u know that the primary function of uart is parallel to serial conversion while transmitting and serial to paralel conversion while receiving..I was wondering if someone could tell me as how can i do a parallel to serial conversion and vice versa without using a clock. Thank You SHASHI


Slightly unmatched UART frequencies

Started by valentin tihomirov in comp.arch.fpga14 years ago 38 replies

UART is used to transfer a byte in serial form bit-by-bit. I know that 10% deriviations in frequencies of transmitter and receiver are...

UART is used to transfer a byte in serial form bit-by-bit. I know that 10% deriviations in frequencies of transmitter and receiver are permissible. I was learnt that UARTs synchronyze at the falling edge (1to0) of start bit; hence, there should allow for transfer of a stream of bytes of arbitrary length. I have developed a simple UART. It's receiver and transimtter run at 9600 bps with 16x...


How to trigger write signal and read sigal

Started by ZHI in comp.arch.fpga11 years ago

I want to test uart function only. Data is transmitted from matlab to FPGA board(uart), and is sent back to matlab. I have a question here. How...

I want to test uart function only. Data is transmitted from matlab to FPGA board(uart), and is sent back to matlab. I have a question here. How can I trigger the write signal and read signal of UART? Thanks in advance. \zhi


How to use UART on Spartan 3E Starter Kit

Started by Jay in comp.arch.fpga10 years ago 4 replies

Hello, Can anybody help me with some reference designs, through which I can get an insight to using UART on Spartan 3E Starter Kit ? I...

Hello, Can anybody help me with some reference designs, through which I can get an insight to using UART on Spartan 3E Starter Kit ? I have downloaded few reference designs which uses UART but I am not getting exact hands on experience. Thanks in advance. Jayesh :-|


uart / Nios2

Started by HB in comp.arch.fpga12 years ago 3 replies

Hi, I 'm trying to use UART with NIOS2 (Stratix). I would like to send a message to Hyperterminal. (not with JTAG_UART, and not with NIOS IDE...

Hi, I 'm trying to use UART with NIOS2 (Stratix). I would like to send a message to Hyperterminal. (not with JTAG_UART, and not with NIOS IDE console) Could you help me ?. (free example could be perfect !). Regards, BH.