uart / Nios2

Started by HB in comp.arch.fpga16 years ago 3 replies

Hi, I 'm trying to use UART with NIOS2 (Stratix). I would like to send a message to Hyperterminal. (not with JTAG_UART, and not with NIOS IDE...

Hi, I 'm trying to use UART with NIOS2 (Stratix). I would like to send a message to Hyperterminal. (not with JTAG_UART, and not with NIOS IDE console) Could you help me ?. (free example could be perfect !). Regards, BH.


How to comm with Altera JTAG UART (from custom host software)?

Started by Kolja Waschk in comp.arch.fpga15 years ago 2 replies

Hi, is there any way to communicate with software running on a NIOS2 SOPC through JTAG from custom software on a Host PC? maybe via JTAG UART...

Hi, is there any way to communicate with software running on a NIOS2 SOPC through JTAG from custom software on a Host PC? maybe via JTAG UART etc... Would be nice if nios2-terminal provided a method to connect to the JTAG UART from own applications through Unix or TCP sockets, or something similar. Would be perfect if there was a public specification or source code example how to access ...


Reading out LUTM content

Started by Reinhard in comp.arch.fpga9 years ago

Hi all, Following problem: We have an Xilinx Virtix 5, having an implementation running on it. What we want to do, is to read out all the...

Hi all, Following problem: We have an Xilinx Virtix 5, having an implementation running on it. What we want to do, is to read out all the bits (or the state) of the different LUTM cells. At the moment, we are outputting this information with the help of an UART module. However, we are wondering whether we could completely get rid of the UART and use the JTAG instead somehow. So wit...


(Stupid/Newbie) Question on UART

Started by Anonymous in comp.arch.fpga17 years ago 33 replies

Hello, I am wondering if someone could clear this doubt for me, in case of UART, the clock speed is 1.8432 MHZ, however it is able to...

Hello, I am wondering if someone could clear this doubt for me, in case of UART, the clock speed is 1.8432 MHZ, however it is able to transmit maximum of 115,200 bps, however even if we are able to transmit at 1 bit per cycle we should be able to transmit at 1,843,200 bps. What is the rationale for making something go slowly, when it can go much faster. PS, I really could not find an...


RS232 Uart for Virtex-II Pro

Started by Eric in comp.arch.fpga16 years ago 3 replies

Does anyone know if there's a ready-to-use rs232 uart in vhdl for the Virtex-II pro fpga? We have done some designs in ISE, and hope to display...

Does anyone know if there's a ready-to-use rs232 uart in vhdl for the Virtex-II pro fpga? We have done some designs in ISE, and hope to display results in a terminal window. Thanks.


video stream transfer via UART and Bluetooth in FPGA

Started by Narendra Sisodiya in comp.arch.fpga13 years ago 4 replies

I need to send video stream over a bluetoth link , case 1 ) the video lise is some format (suggest a easy format) in CF compact flash card , I...

I need to send video stream over a bluetoth link , case 1 ) the video lise is some format (suggest a easy format) in CF compact flash card , I need to read this file and send it through UART, Kindly give me any link to do this case 2 ) I have vidoe starter kit and video is need to be captured and processed and then I will send it through UART which case will be easy ? another problem ...


Re: rs232 uart: testbench vs real world, and the missing first letter.

Started by Jonathan Bromley in comp.arch.fpga13 years ago 1 reply

On Thu, 05 Feb 2009 00:42:41 +0000, Jonathan Bromley wrote: > I've written a data > generator to create your message strings [...] > And...

On Thu, 05 Feb 2009 00:42:41 +0000, Jonathan Bromley wrote: > I've written a data > generator to create your message strings [...] > And I've rewritten the top module to use this alongside > your existing UART transmitter. You should be able to > try it out rather easily and tell me whether it works - > I've only tried it in simulation so far, but I'll try > it on my little demo board tomor


Re: rs232 uart: testbench vs real world, and the missing first letter.

Started by Jonathan Bromley in comp.arch.fpga13 years ago 2 replies

On Wed, 4 Feb 2009 05:42:01 -0800 (PST), jleslie48 wrote: > my serial line ( rs232_tx_data) idles for 955ns based on the > whole system...

On Wed, 4 Feb 2009 05:42:01 -0800 (PST), jleslie48 wrote: > my serial line ( rs232_tx_data) idles for 955ns based on the > whole system waiting for > uart_reset_buffer. If that is not enough, then that was not made > clear to me. It's nowhere near enough to make me feel safe. Any real UART receiver - like the one in your PC - is quite likely to get messed-around by whatever happens i


sopc -apex20ke1500xxxx

Started by nmn in comp.arch.fpga15 years ago

hi all i hav a sopc board(with apex20ke1500xxx fpga),altera quartus ii tool, i got a sof file, now the board is having uart,sdram and...

hi all i hav a sopc board(with apex20ke1500xxx fpga),altera quartus ii tool, i got a sof file, now the board is having uart,sdram and etc., stuffs now i hav been assigned a work of testing my uart design(verilog) on this board, i am in confusion of procedures if possible how? bye


Re: rs232 uart: testbench vs real world, and the missing first letter.

Started by Jonathan Bromley in comp.arch.fpga13 years ago 1 reply

On Thu, 5 Feb 2009 21:58:31 -0800 (PST), rickman wrote: [of the Ken Chapman UART design that jleslie48 is using] > Wow! I know it is...

On Thu, 5 Feb 2009 21:58:31 -0800 (PST), rickman wrote: [of the Ken Chapman UART design that jleslie48 is using] > Wow! I know it is possible and will potentially give you the optimum > size design, but I have never actually seen a unit that was 100% > instantiated. Technically this is VHDL. But for all practical > purposes, this is a schematic expressed in text. Yes, I was pretty stagg


EDK:input to microblaze

Started by Anonymous in comp.arch.fpga16 years ago 7 replies

hi, I want to input data from outside the board to the microblaze.can i do it using uart in my design?Can i make this data come from...

hi, I want to input data from outside the board to the microblaze.can i do it using uart in my design?Can i make this data come from the hyperterminal to the uart and from uart to microblaze?In such a system what ever output microblaze sends outside the board can come on the hyperterminal.Can this output data go to a file? Thanx


What MAXIM chip is used on Spartan 3E 1600E Microblaze Board for RS232 communication?

Started by Alex in comp.arch.fpga12 years ago 12 replies

Hello All, I have started using Xilinx Spartan3E 1600E Microblaze Development Board and want to use its RS232 facility in my project. This...

Hello All, I have started using Xilinx Spartan3E 1600E Microblaze Development Board and want to use its RS232 facility in my project. This board has two RS232 connectors but I cannot figure out what UART it uses. I was searching for UART chip on the board (I was actually searching for a MAXIM chip) and have seen none. The Xilinx board's manual (ug257) does not say what particular UART is ...


nios2 / terminal

Started by HB in comp.arch.fpga16 years ago 1 reply

Hi, Do you have experience with nios2 and a specific terminal (hyperterminal, tera pro, or others) ?. I have problem to only have an easy...

Hi, Do you have experience with nios2 and a specific terminal (hyperterminal, tera pro, or others) ?. I have problem to only have an easy printf message !!.... I 'm using Stratix(10) Altera Develop KIT with UART "console" DB9. I'm using example 'standart' (this example have an uart) In the Nios software I'm using example 'hello_word". jtag_uart is OK, I receive this message 'hello_wo...


UART CORE FOR NIOS

Started by Anonymous in comp.arch.fpga16 years ago 3 replies

We are working on a proect using NIOS which needs to talk to the PC Via a serial port, However we found that the core supplied by AILTERA...

We are working on a proect using NIOS which needs to talk to the PC Via a serial port, However we found that the core supplied by AILTERA seems to work at slow speed only even the core is runing at 50mhz, it seems that it cannot run faster than 2400baud, Any body has silmiar problems? We are trying a UART with FIFO but still struggling with it. Any ideas/ suggestion?


Many UARTs on Avalon bus with NIOS cpu

Started by Anonymous in comp.arch.fpga17 years ago

I am looking for a nice idea of hooking up many (12) simplified UART devices to NIOS II cpu using Avalon bus and fitting everything in Altera...

I am looking for a nice idea of hooking up many (12) simplified UART devices to NIOS II cpu using Avalon bus and fitting everything in Altera Cyclone FPGA. The problem I see is all UARTs are using one baudrate generator with 8 outputs for TX/RX clocks selectable for each UART. What would be the best way of incorporating such components into one SOPC? Or... maybe is there a way to make a mega-...


UART receiver

Started by promach in comp.arch.fpga4 years ago 1 reply

Hi, I am working on UART receiver. As of now, I am stucked at http://paste.ubuntu.com/25720292/ I could not find a proper hardware writing style...

Hi, I am working on UART receiver. As of now, I am stucked at http://paste.ubuntu.com/25720292/ I could not find a proper hardware writing style to continue with line 14 the overall hierarchy : https://i.imgur.com/lVEtKXT.png module sampling_strobe_generator(clk, start_detected, sampling_strobe); // produces sampling signal for the incoming Rx input clk, start_detected; output r...


Got UART Working!!! need syntax help with using ascii/buffer scheduling.

Started by jleslie48 in comp.arch.fpga13 years ago 9 replies

Ok finally, I've got a working UART. I initially had it monitor the receive line and echo back out the character that it received. I then...

Ok finally, I've got a working UART. I initially had it monitor the receive line and echo back out the character that it received. I then changed it so that just sent the the letter 'U' by stuffing the hex code in the TX_DATA_IN buffer: TX_DATA_IN( 7 DOWNTO 0 )


UART with FIFO -> CPLD / FPGA / ?

Started by Martin Maurer in comp.arch.fpga17 years ago 2 replies

Hello, i want to create a special UART with a FIFO (at least 64 Bytes deep, perhaps bigger). Can someone tell me, how a FIFO can be...

Hello, i want to create a special UART with a FIFO (at least 64 Bytes deep, perhaps bigger). Can someone tell me, how a FIFO can be implemented in hardware ? Is is "simply" an array of bytes, with two counters: one for filling it in and one for reading out ? Or is there a better approach ? At the moment i have only knowledge in ABEL with XILINX CPLD (XC95) series. Is it the right way to...


simulating code loading in memory and jumping to memory

Started by sjulhes in comp.arch.fpga16 years ago 7 replies

Hi, I use EDK/ISE/Modelsim. Just want to make some tests and learn on this subject, i would like to create a small system like...

Hi, I use EDK/ISE/Modelsim. Just want to make some tests and learn on this subject, i would like to create a small system like : microblaze external sdram or ddr uart. The code I will have is to loop on a xil_printf of hello world on the UART. So I will generate an elf file to do this. Secondly, I will write some kind of bootloader in BRAM that will read the elf file under models...


EDK frequency problem

Started by fmostafa in comp.arch.fpga13 years ago 1 reply

hi every body, Iam using EDK 9.2 in a small project for the uart , and i started the project with 100 mhz for the processor and 50 mhz for...

hi every body, Iam using EDK 9.2 in a small project for the uart , and i started the project with 100 mhz for the processor and 50 mhz for buses , and i want to change the frequency for the buses to 66 mhz , i did this before for 33 mhz , but in the case of 66 mhz nothing work, all i did i change the C_CLKDV_DIVIDE to 1.5 instead of 2 and the uart frequency to 66666667 instead of 5000000...