Timing Issues in Quartus design

Started by pjjones in comp.arch.fpga17 years ago 1 reply

I'm facing some timing problems and I'm not really sure how to proceed. In this design, there is a Nios processor, and a good bit...

I'm facing some timing problems and I'm not really sure how to proceed. In this design, there is a Nios processor, and a good bit of supporting components to interface with an external DSP (close to 9,000 LEs total). There are two UART/fifo components (written in-house) to support communication between the DSP and some other components. There were no problems until I added a third UART -...


building a card reader into a virtex 2 or 5 based FPGA device.

Started by jleslie48 in comp.arch.fpga12 years ago 6 replies

Sorry to start from scratch yet again, but I don't know where to begin. In the past I've had log file info dump out onto a UART...

Sorry to start from scratch yet again, but I don't know where to begin. In the past I've had log file info dump out onto a UART as necessary. The UART is slow, and requires an additional device to capture the datastream. I want to be able to write to a removable memory stick, or compact flash card, but I don't have any idea how to do it. When the FPGA is powered up it should start a ...


Inconsistant compilations with quartus

Started by Daniel in comp.arch.fpga17 years ago 2 replies

I are having truoble with quartus comiling my designs. I did a design in schematic and it worked correctly until I inserted a AHDL uart at witch...

I are having truoble with quartus comiling my designs. I did a design in schematic and it worked correctly until I inserted a AHDL uart at witch time the uart was unstable every thing else worked fine. My supplier advised me that I shouldn't use the schematic as it doesn't compile properly and things can work one time and then do a small change and they do not the next. So I wrote it all out ...


Interconnection of multiple cores

Started by sebas in comp.arch.fpga11 years ago 5 replies

Hi, I have a design in which I use multiple cores for connecting to different interfaces: SPI, I2C, UART, etc. Each interface outputs the data...

Hi, I have a design in which I use multiple cores for connecting to different interfaces: SPI, I2C, UART, etc. Each interface outputs the data to memory. I want to be able to both transmit data from the interface cores, read data from them and configure them (baud rate for example for UART). How can I do this? Can I use the Wishbone bus and build a master core to drive the operations, the inter...


OPB_MDM as UART in a PowerPC design

Started by Pablo in comp.arch.fpga14 years ago

Hi everybody, I work with a VirtexIIPro in a design with PowerPC processor. I have some problems with the opb_mdm to work as uart. My board...

Hi everybody, I work with a VirtexIIPro in a design with PowerPC processor. I have some problems with the opb_mdm to work as uart. My board has not RS232 peripheral, so I used a OPB_MDM and a PLB2OPB bridge. This solution does not seem to be enough and I receive quite a lot error message such as "Unable to connect processor" in my XMDSTUB console. I explain what I do when I download the ...


simulation works fine but the actual chip doesnt work

Started by Anonymous in comp.arch.fpga15 years ago 6 replies

Hi all, I am working on a chip design, where the frontend is interfaced to PCI bus and the backend has asynchronous FIFOs and a UART. I load...

Hi all, I am working on a chip design, where the frontend is interfaced to PCI bus and the backend has asynchronous FIFOs and a UART. I load the data into the FIFO at 33 MHz and then read it at 40 mhz and pass it to the UART module to transmit the data out. The design works great in simulation, but it is giving me entirely different results when i check it through a logic analyzer on the a...


UART RS232 "hello world" program trial and terror.

Started by jleslie48 in comp.arch.fpga13 years ago 31 replies

Ok, continuing with the RS232 and Ricks pseudo code for sending out a 16 character...

Ok, continuing with the RS232 and Ricks pseudo code for sending out a 16 character message: -------------------------------------------------------------------------------- constant TstData : string(0 to 15) := "Testing 1, 2, 3!"; signal TxCntr : integer range 0 to 16; TxNxtData


RS232 UART: Hello world program finally done.

Started by jleslie48 in comp.arch.fpga13 years ago

Well through trial and terror I finally have a reasonable "hello world" program that I think is worthy. Thanks goes out big time to Jonathan...

Well through trial and terror I finally have a reasonable "hello world" program that I think is worthy. Thanks goes out big time to Jonathan Bromley and Rick for all their input. Jonathan's finite state machine, JB_Data_Generator in combination with the UART example from Xilinx were the combination that allows a programmer to get his first program fpga program running where he can print "...


UART Receiver Parity Check

Started by Anonymous in comp.arch.fpga14 years ago 2 replies

Hello, I'm trying to learn VHDL and here I'm adding a parity bit to Ben Cohen's UART Receiver. RxReg(9) is incoming parity bit...

Hello, I'm trying to learn VHDL and here I'm adding a parity bit to Ben Cohen's UART Receiver. RxReg(9) is incoming parity bit from transmitter side. A 0 output at Parity_err means no parity error detected and otherwise. The receiver has to match the incoming parity bit with its own parity bit which is calculated using XOR of its data byte, RxReg(8 downto 0). My statement below is giving m...


RS232 transmitter core--Xilinx xapp223(Chapman's macro)

Started by Vivek Menon in comp.arch.fpga15 years ago 6 replies

I came across the Xilinx application xapp223 for the implementation of the UART cores. I have been trying various implementations of...

I came across the Xilinx application xapp223 for the implementation of the UART cores. I have been trying various implementations of UART transmitter cores and I am trying to implement this macro on a Xilinx Virtex-II Pro 7 FPGA FF672 board. Now, I am using a 100 MHz clock, which gets divided by 162 to provide the exact clock for a baud rate of 38,400. I have also declared the uart_tx as a bl...


Altera NIOS2 50.0 SOPC periphals broken???

Started by Jedi in comp.arch.fpga16 years ago 3 replies

Trying to run some small system with NIOS2 and timer/uart periphal... 1. Problem...regardless what I set for the UART as fixed BAUD it always ...

Trying to run some small system with NIOS2 and timer/uart periphal... 1. Problem...regardless what I set for the UART as fixed BAUD it always stays at 115200 baud... 2. Adding a timer with all features enabled and 10msec period it doesn't allow me to start/stop and to modify period time... So I assume other SOPC components are broken as well in NIOS2 5.0? /jedi


Re: Got UART Working!!! need syntax help with using ascii/buffer scheduling.

Started by Brian Drummond in comp.arch.fpga13 years ago

On Tue, 27 Jan 2009 20:22:35 +0000, Jonathan Bromley wrote: > On Tue, 27 Jan 2009 08:26:44 -0800, Mike Treseler wrote: > > > The...

On Tue, 27 Jan 2009 20:22:35 +0000, Jonathan Bromley wrote: > On Tue, 27 Jan 2009 08:26:44 -0800, Mike Treseler wrote: > > > The reference design here: > > http://mysite.verizon.net/miketreseler/ > > is a single process > > (aka: sequential, linear, single threaded) > > vhdl design that just happens to be a uart. > > Mike, > > you know I'm a strong supporter of


Problem with the SOPC-Builder from Altera

Started by Roman Leitner in comp.arch.fpga17 years ago 1 reply

Hello , got a problem with the SOPC-Builder from Altera. I made a new Project in Quartus2, and added a MEGAFUNCTION from SOPC. In the SOPC i...

Hello , got a problem with the SOPC-Builder from Altera. I made a new Project in Quartus2, and added a MEGAFUNCTION from SOPC. In the SOPC i added the NIOS2 Core, OnChip Memory, Jtag UART and Serial UART. When I try to generate the code, an error occurs. here is the whole logfile: Altera SOPC Builder Version 4.10 Build 208 Copyright (c) 1999-2004 Altera Corporation. All rights r...


integrate microblaze in ISE and VHDL code

Started by rody786 in comp.arch.fpga7 years ago

Dear all, I'm beginner to use microblaze. I made a simple program to read two numbers from uart and add them using microblaze. For further...

Dear all, I'm beginner to use microblaze. I made a simple program to read two numbers from uart and add them using microblaze. For further purposes I want to integrate the microblaze as subcomponnet in a top level VHDL code, I need to get the two numbers read from the uart (for the microblaze operation) in another vhdl component. How could I do that?? Thanks -----------...


How to control the uart

Started by ZHI in comp.arch.fpga15 years ago 4 replies

Here is my general idea.I generate a matrix in Matlab. I want to transmit the numbers in matrix into FPGA. And these numbers will be sent to an...

Here is my general idea.I generate a matrix in Matlab. I want to transmit the numbers in matrix into FPGA. And these numbers will be sent to an algorithm implemented FPGA board. The algorithm will deal with these numbers and new result is sent back to PC(Matlab, I want to compare the result from MATLAB). I know transmitting these numbers to FPGA board. I need a UART. I have one. I also hav...


microblaze firmware + UART handshaking blues

Started by Anonymous in comp.arch.fpga14 years ago 14 replies

Hi, I am currently working on a microblaze v6.00 core on FPGA and am developing an algorithm. This is what I am doing 1) matlab on PC...

Hi, I am currently working on a microblaze v6.00 core on FPGA and am developing an algorithm. This is what I am doing 1) matlab on PC sends data to microblaze (FPGA) via UART. RS232 hardware handshaking is deployed here. 2) the algorithm runs on microblaze to process the input data 3) microblaze sends the data back to matlab on PC. the setup I am working on works perfectly on a p...


C-Compiler for free VHDL controller core ?

Started by Peter Winkler in comp.arch.fpga15 years ago 14 replies

Hi ! I would like to use a free microcontroller core on my Spartan 3 FPGA. There are quite some free cores available, but I would like to...

Hi ! I would like to use a free microcontroller core on my Spartan 3 FPGA. There are quite some free cores available, but I would like to know what everybody is using. It would be great if the free core would be supported by gcc or some other free C-Compiler. I also need a UART, so what I am searching for is: * free FPGA controller core (with UART) * C-Compiler supporting it Do...


Primitive debuggable UART interface to a Nios within a multi-Nios system

Started by Ang Zhi Ping in comp.arch.fpga7 years ago 19 replies

I am working on an IP core with a Nios controller. This IP will eventually be integrated into a multi-Nios system. I also foresee that this IP...

I am working on an IP core with a Nios controller. This IP will eventually be integrated into a multi-Nios system. I also foresee that this IP will not be JTAG debuggable because the integrator will be using the JTAG facility on a higher level Nios controller. In this case I have planned to include a UART interface, which allows the integrator to do on-the-fly primitive debugging with t...


spart 3 uart example

Started by dollaz in comp.arch.fpga17 years ago 2 replies

I am using the spartan 3 and want to read in data from the hyperterminal. I wanted to know if someone had or could show me an example of how to...

I am using the spartan 3 and want to read in data from the hyperterminal. I wanted to know if someone had or could show me an example of how to do this. thanks


How to connect an IP to OPB bus??

Started by Sandip in comp.arch.fpga15 years ago 2 replies

Hi, I am working with Virtex-4. I have generated a VHDL code and need it to communicate it with Power PC and some other cores such as UART...

Hi, I am working with Virtex-4. I have generated a VHDL code and need it to communicate it with Power PC and some other cores such as UART and I2C which sits on the OPB. I am willing to connect my IP core to this bus. can anyone help me how to do this?? Thanks and regards, Sandip