EDK: OPB Question

Started by Anonymous in comp.arch.fpga16 years ago 1 reply

Hi all, I have two questions regarding the OPB usage. 1) why is it the microblaze connects to the IOPB port to the OPB bus when running from...

Hi all, I have two questions regarding the OPB usage. 1) why is it the microblaze connects to the IOPB port to the OPB bus when running from internal memory (BRAM) ? the program runs only from the ILMB isn't it? 2) PLB-OPB bridge , the PPC405 reference guide says that the PLB should be used for fast bus transactions and that the OPB is to be used for slower peripherals (GPIOs/UART etc.). My...


CMUcam2 and a XUP-V2Pro

Started by Anonymous in comp.arch.fpga14 years ago

Greetings all, Has anyone connected and used a CMUcam2 to a Digilent XUP-V2Pro FPGA board? If so, how did you do it? That is what module or...

Greetings all, Has anyone connected and used a CMUcam2 to a Digilent XUP-V2Pro FPGA board? If so, how did you do it? That is what module or connector did you use? I am trying to use the Uart lite IP through the low-speed expantion headers? Let me know of any questions or thoughts you may have. Thank you, Rob Harrell


EDK oddity

Started by MS in comp.arch.fpga18 years ago

So I have a Memec P7 evaluation board with the EDK and a Parallel 4 download cable. We are doing something very basic here to just get our feet...

So I have a Memec P7 evaluation board with the EDK and a Parallel 4 download cable. We are doing something very basic here to just get our feet wet. All we are doing is writing to the UART a simple hello world program. We wrote some C code, and then stepped through the base system builder using this board. We went thru all the steps in the EDK and downloaded right from the EDK to the bo...


EDK Microblaze project without OPB?

Started by JD Newcomb in comp.arch.fpga14 years ago 2 replies

Hi, all. Is it known to be possible to create a Microblaze system without the OPB? For example, say I have 1 MicroBlaze with 16KB of d&i...

Hi, all. Is it known to be possible to create a Microblaze system without the OPB? For example, say I have 1 MicroBlaze with 16KB of d&i BRAM, but I don't necessarily need the off-chip SDRAM or UART (or any OPB slave peripheral at all), so I don't include the OPB. And say it's part of a larger network to justify not needing the OPB for any peripherals. Currently, my 8.2 version has an...


Picoblaze, UART: need help!!

Started by preet in comp.arch.fpga15 years ago 1 reply

Thanks so much to all who replied to my previous messages I appreciate your concern. Please help me on this. I have written the code for my...

Thanks so much to all who replied to my previous messages I appreciate your concern. Please help me on this. I have written the code for my encoder below. It is synthesizable and has no errors. What i want to do is after programming the FPGA(Spartan3 starter kit), I want to check the results from the harware. Means using LEDs for 3 bit output and switch for the input. My code also c...


Re: EDK tutorial?????

Started by Matthew E Rosenthal in comp.arch.fpga17 years ago 2 replies

I would rather not use the ultracontroller design anymore. I want to create a EDK project from scratch, add a plb buss, add a few...

I would rather not use the ultracontroller design anymore. I want to create a EDK project from scratch, add a plb buss, add a few peripherials(gpio and uart). Doesnt sound like i am asking for the world but i am having a tough time finding some simple instructions on how to do it. anybody know where i can find some instructions for this? Matt On Thu, 5 Aug 2004, Symon wrote: > M


Re: rs232 uart: testbench vs real world, and the missing first letter.

Started by Jonathan Bromley in comp.arch.fpga13 years ago 2 replies

On Fri, 6 Feb 2009 12:56:38 -0800 (PST), jleslie48 wrote: > whoa!!!! hold on there! now things are getting interesting! Yup. You've given...

On Fri, 6 Feb 2009 12:56:38 -0800 (PST), jleslie48 wrote: > whoa!!!! hold on there! now things are getting interesting! Yup. You've given me an excuse to waste a lot of time playing around with my little Spartan-3 kit :-) > thanks for the correct syntax: > op_MESSAGE & tua("Hello"&CR&LF) & EOM & There's no reason in principle why the generic should not be a string; but, as I pointe


Re: Spooling from FPGA to the PC

Started by Daniel Leu in comp.arch.fpga17 years ago

Have a look at FT2232C from FTDIchip.com. It is a simple USB slave controller that comes with the USB drivers. These drivers provide an UART...

Have a look at FT2232C from FTDIchip.com. It is a simple USB slave controller that comes with the USB drivers. These drivers provide an UART com port on your PC. So interfacing this with your application is really easy. If your USB bus is not busy with other peripherals, you can get up to 8Mbit/s. So this should be sufficient for your application. /Daniel SneakerNet wrote: > Hi All


XMD and xilmfs help

Started by Joseph in comp.arch.fpga16 years ago 1 reply

Hello, I have a board with 256M of RAM and a V2P30. Designed a simple system in EDK with the RAM partitioned into 2 equal parts. Compiled a...

Hello, I have a board with 256M of RAM and a V2P30. Designed a simple system in EDK with the RAM partitioned into 2 equal parts. Compiled a .elf to live in one half and want to use the other half for a filesystem. The .elf runs fine in the sense that I get the "Usage: " message from it via the UART when it realizes it doesn't have any input files. I have trouble when I try and incorpor...


rs232 uart: testbench vs real world, and the missing first letter.

Started by jleslie48 in comp.arch.fpga13 years ago 21 replies

From previous thread: +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ My first cleanup was to at least reduce the strings to...

From previous thread: +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ My first cleanup was to at least reduce the strings to something that I could actually read. The side effect being that the first character of the string got clobbered and that answer will reside in the spagetti code that you pointed out. Meantime its not immediately obvious to me from the testbench:...


Re: rs232 uart: testbench vs real world, and the missing first letter.

Started by Jonathan Bromley in comp.arch.fpga13 years ago

On Tue, 10 Feb 2009 11:44:43 -0800 (PST), jleslie48 wrote: > > It will still be a long way from Turing-completeness :-) > > and a very long...

On Tue, 10 Feb 2009 11:44:43 -0800 (PST), jleslie48 wrote: > > It will still be a long way from Turing-completeness :-) > > and a very long way from doing any useful DSP :-( > but being able to scan a rom for specific signals, (label) > and caching them you don't consider a worthwhile process of a > DSP? OK, OK, I retract the cheap insult... the serious point behind it was that incremental


NMEA Decoder/Display

Started by al99999 in comp.arch.fpga16 years ago 8 replies

Hi, Has anybody ever designed anything to decode and display GPS NMEA data coming out in ascii form from a UART? Any ideas of where to...

Hi, Has anybody ever designed anything to decode and display GPS NMEA data coming out in ascii form from a UART? Any ideas of where to start or how to go about decoding comma delimted ascii strings? Thanks, Al


Help =(

Started by Zhane in comp.arch.fpga13 years ago

I've problem with my codes. I'm trying to make a LPC Bus interface with my Spartan 3E to tap the bus traffic coming from keypresses. I'm...

I've problem with my codes. I'm trying to make a LPC Bus interface with my Spartan 3E to tap the bus traffic coming from keypresses. I'm using the LCLK from the bus and the FPGA 50Mhz clock for my processes. I'm using those expansion connectors to probe the bus, storing it into a 2-clock FIFO, and a uart which reads from the FIFO and send it to the PC I've simulated it on my modelsim ...


Re: Got UART Working!!! need syntax help with using ascii/buffer scheduling.

Started by Brian Drummond in comp.arch.fpga13 years ago

On Tue, 27 Jan 2009 18:17:41 -0800 (PST), jleslie48 wrote: > On Jan 27, 7:08?pm, Brian Drummond > wrote: > ~Seriously; if you can...

On Tue, 27 Jan 2009 18:17:41 -0800 (PST), jleslie48 wrote: > On Jan 27, 7:08?pm, Brian Drummond > wrote: > ~Seriously; if you can treat this "bbfifo.vhd" as a black box, go > ahead > ~ and use it. > > you're the second person today to tell me that. That's actually a bit > of a > comfort. So any throttling of the 16 bit buffer will hav


Chasing Bugs in the Fog

Started by rickman in comp.arch.fpga8 years ago 9 replies

I have a bug in a test fixture that is FPGA based. I had thought it was in the software which controls it, but after many hours of chasing it...

I have a bug in a test fixture that is FPGA based. I had thought it was in the software which controls it, but after many hours of chasing it around I've concluded it must be in the FPGA code. I didn't think it was in the VHDL because it had been simulated well and the nature of the bug is an occasional dropped character on the receive side. Who can't design a UART? Well, it could be...


looking for dev kit for ProAsic3

Started by alb in comp.arch.fpga7 years ago 7 replies

Hi everyone, I'm looking for a dev kit for a ProAsic3 A3PE3000 (microsemi) with some minimum amount of functional blocks around...

Hi everyone, I'm looking for a dev kit for a ProAsic3 A3PE3000 (microsemi) with some minimum amount of functional blocks around (volatile/non-volatile memory, few peripherals like UART, USB, SPI ...). So far I've found this interesting piece http://www.skylabs.si/DevBoard_PicoSky_a3pe3000.aspx but something simpler can work as well. The main reason is to use it as a testbed for ou...


Help to SImulate Uart TX

Started by Zhane in comp.arch.fpga13 years ago 18 replies

I'm using the following code. I've managed to make it work on my fpga before. but when I try to simulate on my modelsim, it seems that it never...

I'm using the following code. I've managed to make it work on my fpga before. but when I try to simulate on my modelsim, it seems that it never gets into the statemachine. I've configured the settings for a 50Mhz clock...also set the config for model sim to be 10ns 10ns for clock high and low. How should I go about simulating this? --------------------------------------------------...


VHDL variable setup and propogations

Started by Anonymous in comp.arch.fpga18 years ago 1 reply

Greetings, I am having a strage time with some code I recently wrote to implement a UART - the code is working fine now, but a problem cropped...

Greetings, I am having a strage time with some code I recently wrote to implement a UART - the code is working fine now, but a problem cropped up that is baffling me. This design is being synthesized in Xilinx ISE 5 and implemented into a Spartan-II XD2S50 device. I'm on something of a learning curve with things right now so please go easy on me! :D when 10 => -- Stop Bit


xps error never seen before: google reveals nothing; help!

Started by N.V. Chandramouli in comp.arch.fpga14 years ago 4 replies

(reposting with catchier subject line and some changes...) Hi, We are trying to run the "Virtex4_PPC_Example_9_1" example program from...

(reposting with catchier subject line and some changes...) Hi, We are trying to run the "Virtex4_PPC_Example_9_1" example program from EDK9.1.2 that has TestInterrupt.c routine (timer interrupt driving the LEDs and UART interface displaying the status.) The LEDs on the board appear to flash quickly, but we're unable to speed up or slow down the clock using the 'f' , 's' inputs via th...


Re: Got UART Working!!! need syntax help with using ascii/buffer scheduling.

Started by Jonathan Bromley in comp.arch.fpga13 years ago 7 replies

On Mon, 26 Jan 2009 17:26:25 -0800 (PST), jleslie48 wrote: > Yeah I'm gonna fall into that linear C programming trap a lot. [...] > never...

On Mon, 26 Jan 2009 17:26:25 -0800 (PST), jleslie48 wrote: > Yeah I'm gonna fall into that linear C programming trap a lot. [...] > never liked threads ;) Time to change, if you're trying to use VHDL and hardware. > the SelectCntr process as you pseudo coded up, will use its clk > to make the looper go through the the TstData, but the routine is > going to > need a governor of some sorts