UART receiver

Started by Konstantin Dols in comp.arch.fpga17 years ago 7 replies

Greetings ! I'm looking for a simple RS232 UART16550 receiver for my tiny cyclone board for different baudrates, 8databits, 1stop&startbit...

Greetings ! I'm looking for a simple RS232 UART16550 receiver for my tiny cyclone board for different baudrates, 8databits, 1stop&startbit and no(!) partity and handshake stuff. I found several free VHDL implementations in the net but compared to what I need they are to complicated and appear like shooting with missiles on birds ;-) The entity might have a simple structure...


Re: rs232 uart: testbench vs real world, and the missing first letter.

Started by Jonathan Bromley in comp.arch.fpga13 years ago 1 reply

On Fri, 6 Feb 2009 09:39:09 -0800 (PST), jleslie48 wrote: > 16.67Mhz is generated by 1/6th of the 100MHZ. 1/9th of that is > exactly that,...

On Fri, 6 Feb 2009 09:39:09 -0800 (PST), jleslie48 wrote: > 16.67Mhz is generated by 1/6th of the 100MHZ. 1/9th of that is > exactly that, 1/6*/19 == 1/54 of the 1000Mhz. If this machine > can't get that right, I'm gonna be in a whole world of hurt. No, no!!!! I'm not disputing either your or the counter's arithmetic. I'm making a crucial point about HARDWARE. The 16.67MHz clock is u


cpu time of the computation

Started by Terrence Mak in comp.arch.fpga18 years ago 2 replies

Hi, I am new in using the embeded device (VirtexII-Pro) to implement an algorithm. As I want to count the cpu time of the algorithm , I use...

Hi, I am new in using the embeded device (VirtexII-Pro) to implement an algorithm. As I want to count the cpu time of the algorithm , I use the XTime_GetTime(starttime) in the the xtime_l.h library. Also I need to print out the result to a uart by using xil_printf. But the result did not displayed successfully. Please find the program as follows. Is there any step missed? Many thank...


IP core for Bluetooth or Wifi

Started by in comp.arch.fpga12 years ago

Hi, Somebody know where can I found a free IP core for Bluetooth or Wifi? I would like to use it. I don't mind use a USB or UART...

Hi, Somebody know where can I found a free IP core for Bluetooth or Wifi? I would like to use it. I don't mind use a USB or UART module. Best.


ethernet

Started by icegray in comp.arch.fpga16 years ago 10 replies

Hi all, I want to implement ethernet but I have no exprience about ethernet. Can you please recommend some thing. I can use precessor (M16C)...

Hi all, I want to implement ethernet but I have no exprience about ethernet. Can you please recommend some thing. I can use precessor (M16C) or FPGA. I haven't got FPGA development board yet and maybe i can't buy because i have money problem. I think if I use FPGA I don't need ethernet controller If I can write it :). I have try some projects like as uart, I2C on the Nuhorizons CR2 Developme...


embedded powerpc in VirtexII-pro

Started by Terrence Mak in comp.arch.fpga18 years ago 2 replies

Hi, I am new in using the embeded device (VirtexII-Pro) to implement an algorithm. As I want to count the cpu time of the algorithm , I use...

Hi, I am new in using the embeded device (VirtexII-Pro) to implement an algorithm. As I want to count the cpu time of the algorithm , I use the XTime_GetTime(starttime) in the the xtime_l.h library. Also I need to print out the result to a uart by using xil_printf. But the result did not displayed successfully. Please find the program as follows. Is there any step missed? Many thank...


wishbone interface

Started by mkr in comp.arch.fpga13 years ago 3 replies

I ma trying to make my first design (UART) wishbone compliant and looked at wishbone specification and several examples with source code on the...

I ma trying to make my first design (UART) wishbone compliant and looked at wishbone specification and several examples with source code on the net. Though I understand there are some restrictions on multiplexing of address and data bus, tri-state bus etc.. in many cases I hardly see any additional logic in the wishhbone compliant designs other than naming the external signals as per the wish...


FPGA / Virtex II Pro / LWIP

Started by Anonymous in comp.arch.fpga14 years ago 4 replies

Hi, I'd like to get some help from experienced people because I'm really running low on ideas here.. I'm a beginner in FPGA/LwIP and I...

Hi, I'd like to get some help from experienced people because I'm really running low on ideas here.. I'm a beginner in FPGA/LwIP and I can't seem to make it work using Xilinx EDK 8.2i. I've been creating a project using BSB including onewire, uart, emac and the external memory and using PPC. Once I am in the project manager, I did all of the required modifications to boot up on the bram...


Help Needed - LPC Bus Interface

Started by Zhane in comp.arch.fpga13 years ago

I've problem with my codes. I'm trying to make a LPC Bus interface with my Spartan 3E to tap the bus traffic coming from keypresses. I'm...

I've problem with my codes. I'm trying to make a LPC Bus interface with my Spartan 3E to tap the bus traffic coming from keypresses. I'm using the LCLK from the bus and the FPGA 50Mhz clock for my processes. I'm using those expansion connectors to probe the bus, storing it into a 2-clock FIFO, and a uart which reads from the FIFO and send it to the PC I've simulated it on my modelsim ...


XMD crashes on EDK 9.1i

Started by swamy_digital in comp.arch.fpga14 years ago 1 reply

Hello Group Members I am trying to build a simple system consisting of PowerPC405, JTAG, UART, OPB DDR controller, and 16MB External DDR...

Hello Group Members I am trying to build a simple system consisting of PowerPC405, JTAG, UART, OPB DDR controller, and 16MB External DDR memory on a HiTech PPC board. No on-chip BRAMs. I use EDK 9.1/ISE9.1 versions. If I try to launch XMD from EDK GUI, it prints messages detecting the programming cable and quits without printing any error messages. I tried invoking XMD from cygwin she...


Nios Stratix

Started by Benoit in comp.arch.fpga16 years ago

Hi, I'm trying to use a NIOS Kit Eval Board (Stratix10). I would like to do a small application : => incr a counter value in FPGA (VHDH...

Hi, I'm trying to use a NIOS Kit Eval Board (Stratix10). I would like to do a small application : => incr a counter value in FPGA (VHDH code) => convert this value Hex to Dec in FPGA (C code) => use NIOS (UART) to display this Dec value in IHM (SOPC, Hyperterm, ...) I'm searching samples. Could you help me ?. Thanks in advance. Benoit.


simulation troubles

Started by zoin...@mytrashmail.com in comp.arch.fpga16 years ago

hey all, I still can't get the system-wide behavioral simulation of a VirtexII-pro system to work, the entire system is "dead", it is...

hey all, I still can't get the system-wide behavioral simulation of a VirtexII-pro system to work, the entire system is "dead", it is not executing any instructions, or so it seems (what is the init-time for a standard PowerPC generated architecture with no peripherals besides GPIO and UART?) I simulated 10ms but no indication that anything was executed. But now for my real question: ...


UARTlite problem..!!!

Started by Anonymous in comp.arch.fpga16 years ago 1 reply

Hi, I am receiving some data from the uart.I take it and keep it in memory using a pointer.I use the following condition in my code: while...

Hi, I am receiving some data from the uart.I take it and keep it in memory using a pointer.I use the following condition in my code: while (!XUartLite_mIsReceiveEmpty(XPAR_RS232_UART_BASEADDR)) { *uart2ram=XUartLite_RecvByte(XPAR_RS232_UART_BASEADDR); uart2ram++; } then i have to do some processing on the data stored in the memory.I intend to do that after i receive the comple...


Lean Ethernet on Digilent board?

Started by Alfredo in comp.arch.fpga16 years ago 2 replies

Has anyone used the Ethernet add-on module for the Digilent Spartan3 board? http://www.digilentinc.com/info/NET1.cfm I want to back into...

Has anyone used the Ethernet add-on module for the Digilent Spartan3 board? http://www.digilentinc.com/info/NET1.cfm I want to back into design, and instead of doing the same old uart/SERDES design I did years ago, I wanted to do something more challenging. Thanks, *** Alfredo.


Re: rs232 uart: testbench vs real world, and the missing first letter.

Started by Jonathan Bromley in comp.arch.fpga13 years ago 7 replies

On Tue, 3 Feb 2009 13:21:25 -0800 (PST), jleslie48 wrote: > Here's the simulation of the 16 character printout: > >...

On Tue, 3 Feb 2009 13:21:25 -0800 (PST), jleslie48 wrote: > Here's the simulation of the 16 character printout: > > http://jleslie48.com/fpga_uartjl_01/11jlmod/ccuart01/screencap/screencap13_firstislast16.png > > everything looks to me ship-shape. > > I'm gonna have to compare this simulation to a 15 character one. > > anybody see anything? Yes. Jon, how do I put this politely.... (


uBlaze prototype PCB UART issues

Started by mjackson in comp.arch.fpga15 years ago 6 replies

Hello all, Forgive me in advance for the long plea for help. Would anyone be kind enough to troubleshoot my implementation of the EDK 8.1i...

Hello all, Forgive me in advance for the long plea for help. Would anyone be kind enough to troubleshoot my implementation of the EDK 8.1i flow for my production board? I have implemented a good deal of my project firmware on the Spartan 3 evaluation board with great success. However, upon receipt of my 3E based prototype hardware, I have had nothing but problems successfully porting ...


Re: Got UART Working!!! need syntax help with using ascii/buffer scheduling.

Started by Jonathan Bromley in comp.arch.fpga13 years ago 3 replies

On Tue, 27 Jan 2009 09:35:19 -0800 (PST), jleslie48 wrote: > I've got no choice. I have a deliverable to a customer, and > failure is not an...

On Tue, 27 Jan 2009 09:35:19 -0800 (PST), jleslie48 wrote: > I've got no choice. I have a deliverable to a customer, and > failure is not an option. My project worked perfectly fine on a > DSP running C code, but the customer has dictated that It > must run in a pure FPGA environment. So now I'm on the hook > to get it to run on a FPGA. Advice, honestly given, from one Jonathan to another:


75Mhz Spartan3e microblaze

Started by u_st...@yahoo.de in comp.arch.fpga15 years ago 10 replies

hi i hvea a question about implementing a microblaze with ethernet. i'm using a spartan 3e 500 an edk8.2. i created a new project with...

hi i hvea a question about implementing a microblaze with ethernet. i'm using a spartan 3e 500 an edk8.2. i created a new project with a microblaze, an ethernet core, sdram, timer debug module an uart. in the ethernet datasheet it says that in order to be able to use 100MBit the obp bus hast to run at least with 65 MHz. my problem now is the the design wont synthesize with more than 59 MHz...


systemACE compact flash FATFs problems

Started by Bo in comp.arch.fpga17 years ago

I used Xilinx EDK base system builder for an ML310 development board and added UART, sysACE, DDR, BRAM and the design comes up--via an ACE file....

I used Xilinx EDK base system builder for an ML310 development board and added UART, sysACE, DDR, BRAM and the design comes up--via an ACE file. I'm trying to add XilFATFs lib support and make a standalone boot app that will read the vxWorks BSP file from CF and then jump to it. this would allow me to hopefully use soft reboots, bootChange, etc that I cannot now. I added the Xil_FATFs l...


MicroBlaze - how much memory?

Started by RISC taker in comp.arch.fpga18 years ago 1 reply

Hi! How much extra RAM (additional to the pure code size of the user program) do I usually need for a MicroBlaze system?? I am considering...

Hi! How much extra RAM (additional to the pure code size of the user program) do I usually need for a MicroBlaze system?? I am considering MicroBlaze for a Spartan-3 project. Peripherals would be a UART and my own memory mapped peripheral. Assuming that my program can be compiled into less than 300 assembly instructions, it should fit into one single BlockRAM, right? (300 * 32 bits = 9600 b...