XST 9.1 hates VHDL character types

Started by Andy Peters in comp.arch.fpga15 years ago 1 reply

Under ISE 7.1, I did a simple UART module that has a "terminating character" generic, which is of type character. (When the receiver sees that...

Under ISE 7.1, I did a simple UART module that has a "terminating character" generic, which is of type character. (When the receiver sees that terminating character, it asserts a "got terminator" output flag.) XST compiled it and the design works well. I moved to 9.1, and now XST hates the code and craps out: ========================================================================= * ...


chipscope pro

Started by Anonymous in comp.arch.fpga13 years ago

Hello friends, i have written uart module in vhdl,i have verified using xilinx simulator,but now when i have generated the core of icon,ila...

Hello friends, i have written uart module in vhdl,i have verified using xilinx simulator,but now when i have generated the core of icon,ila and vio,i am unable to get correct output in vio console. i have inputs as clk rst write read din(7 downto 0) output as dout(7 downto 0) i have given in xilinx simulator like this clk connected to C9 on kit rst--------------------------...


OpenRisc 1200 on Spartan 3 - problems with stability and enabling cache

Started by Thomas Oehme in comp.arch.fpga16 years ago 4 replies

Hi there, i`m trying to get a SoC runinng, which is based on a OR1200 soft-processor in an Spartan 3 device. At the moment the system is...

Hi there, i`m trying to get a SoC runinng, which is based on a OR1200 soft-processor in an Spartan 3 device. At the moment the system is working (25 MHz, with UART, external SRAM and an SMSC 9118 connected-done with ISE 7.1.04 and 8.1.02). If i`m trying to re-synthesize the whole system with little changes or removed peripherals, the processor seems to get very instable and the executio...


xilinx 8.2 xps debug problems

Started by Ludwig Lenz in comp.arch.fpga15 years ago 2 replies

Hi I am working with an xilinx xup board. 8.2 sp1 ise + 8.2 edk. I am starting creating a design with ppc running from ddr ram, sysace...

Hi I am working with an xilinx xup board. 8.2 sp1 ise + 8.2 edk. I am starting creating a design with ppc running from ddr ram, sysace and uart for output. Starting the debugger with: xmd -xmp system.xmp -opt etc/xmd_ppc405_0.opt with example application works. Closing the project adding a new plb peripherial template with 4x32 registers no interrupts. Reopening the project. Download bi...


NIOS II CFI interface

Started by bjzh...@gmail.com in comp.arch.fpga13 years ago 3 replies

Hi,everybody,I am a fresher of NIOSII,and in the passed days ,I have been familar with the nios II system,also write some test program about the...

Hi,everybody,I am a fresher of NIOSII,and in the passed days ,I have been familar with the nios II system,also write some test program about the gpio,timer,uart and can work properly,today I add the flash controoler(CFI),but it doesn't work.And I use the signal tap to watch the wave and the address bus is active but the read,write and cs is always '1',I don't know why,can someone give me some...


EDK Using External Ports to toggle FPGA pins

Started by Kyle H. in comp.arch.fpga15 years ago 4 replies

Hello All, I am having a hard time understanding EDK ---> FPGA tool flow (I think). I am using EDK/ISE 8.1, testing the Generic Reference...

Hello All, I am having a hard time understanding EDK ---> FPGA tool flow (I think). I am using EDK/ISE 8.1, testing the Generic Reference Design from Memec/Avnet. It is for the Xilinx FX12 mini-module. I have been able to use the drivers supplied to control the LCD screen, rs232 uart and the user LEDs as expected. But when it comes to a specific FPGA pin of my choice I'm getting lost


EDK =>"Virtex4_PPC_Example_9_1" on ubuntu, not able to change LEDs blinking through minicom hyperterminal

Started by N.V. Chandramouli in comp.arch.fpga14 years ago

hi, we are trying to run the "Virtex4_PPC_Example_9_1" example program (that came along with the EDK9.1.2 kit) that has TestInterrupt.c routine...

hi, we are trying to run the "Virtex4_PPC_Example_9_1" example program (that came along with the EDK9.1.2 kit) that has TestInterrupt.c routine (timer interrupt driving the LEDs and UART interface displaying the status.) "We are able to see LEDs flashing on the board but not able to speed up or slow down the clock using the 'f' , 's' inputs through the hyperterminal, which we are expecte...


EDK =>"Virtex4_PPC_Example_9_1" on ubuntu, not able to change LEDs blinking through minicom hyperterminal

Started by N.V. Chandramouli in comp.arch.fpga14 years ago

hi, we are trying to run the "Virtex4_PPC_Example_9_1" example program (that came along with the EDK9.1.2 kit) that has TestInterrupt.c routine...

hi, we are trying to run the "Virtex4_PPC_Example_9_1" example program (that came along with the EDK9.1.2 kit) that has TestInterrupt.c routine (timer interrupt driving the LEDs and UART interface displaying the status.) "We are able to see LEDs flashing on the board but not able to speed up or slow down the clock using the 'f' , 's' inputs through the hyperterminal, which we are expecte...


Re: Got UART Working!!! need syntax help with using ascii/buffer scheduling.

Started by Andreas Ehliar in comp.arch.fpga13 years ago 9 replies

On 2009-01-27, jleslie48 wrote: > I've got no choice. I have a deliverable to a customer, and > failure is not an option. My project worked...

On 2009-01-27, jleslie48 wrote: > I've got no choice. I have a deliverable to a customer, and > failure is not an option. My project worked perfectly fine on a > DSP running C code, but the customer has dictated that It > must run in a pure FPGA environment. So now I'm on the hook > to get it to run on a FPGA. Hi, have you considered simply putting a small proc


mouse to Nios Development kit

Started by clsan in comp.arch.fpga18 years ago 8 replies

Hi all, I am doing a project and using Altera Nios Development kit with Stratix Edition. I need to connect a serial/PS/2 mouse to that...

Hi all, I am doing a project and using Altera Nios Development kit with Stratix Edition. I need to connect a serial/PS/2 mouse to that board . But the board can't get any signal from the mouse, anyone has this experience can share with me?I have already set the UART 2 to 1200 baud rate. Thank you very much. San


Xilinx OCM memory use limitations ?

Started by SJU in comp.arch.fpga14 years ago 2 replies

Hi all, We are building a very simple SOC ( PPC 405, internal memory, UART light) in a V4FX60, with a very simple firmware. The point is...

Hi all, We are building a very simple SOC ( PPC 405, internal memory, UART light) in a V4FX60, with a very simple firmware. The point is that when we use the PLB_BRAM memory, the GDB debugger works fine, but wneh we use the OCM memories, the debugger behaves in astrange way. When we download the file then it goes in a assembly state and executes nothing, I guess it went in some excepti...


OPB_MDM functionality

Started by Pablo in comp.arch.fpga13 years ago

hi, this is my question: Is opb_mdm used to load C code (from executable.elf) from SDRAM?. I have downloaded an aplication (executable.elf) to...

hi, this is my question: Is opb_mdm used to load C code (from executable.elf) from SDRAM?. I have downloaded an aplication (executable.elf) to the Sdram. Due to the fault of a RS232 peripheral, I use opb_mdm as uart. This design seems to work fine with xil_printf and standalone powerpc, but it fails when I use printf or xilkernel. I have increased heap and stack, but problem goes on. So I ...


Re: rs232 uart: testbench vs real world, and the missing first letter.

Started by Jonathan Bromley in comp.arch.fpga13 years ago 1 reply

On Fri, 6 Feb 2009 05:29:44 -0800 (PST), jleslie48 wrote: > > I didn't get an answer to my question yesterday about whether > > the OP's...

On Fri, 6 Feb 2009 05:29:44 -0800 (PST), jleslie48 wrote: > > I didn't get an answer to my question yesterday about whether > > the OP's 16.7MHz divided clock is correctly distributed on > > an internal clock net - i.e., has the Xilinx software > > correctly recognized it to be a clock." > I took some measurements with both the simulator and > the oscilliscope on the ASCII code coming out an


16550 VHDL code

Started by Anonymous in comp.arch.fpga16 years ago 1 reply

Hello, I'm currently writing VHDL code for an Altera cyclone, the EP1C6. One of the modules i need is an 16550 compatible UART which has...

Hello, I'm currently writing VHDL code for an Altera cyclone, the EP1C6. One of the modules i need is an 16550 compatible UART which has to communicate through an ISA bus (PC104). My question is if somebody has the VHDL code for it, or can tell me where i can find code (i've already asked quotes at core suppliers but this is a little bit expensive). Thanks in advance


Re: rs232 uart: testbench vs real world, and the missing first letter.

Started by Jonathan Bromley in comp.arch.fpga13 years ago 3 replies

On Tue, 10 Feb 2009 08:33:14 -0800 (PST), jleslie48 wrote: > I think the next step is > to update the goto functionality to be a goto LABEL...

On Tue, 10 Feb 2009 08:33:14 -0800 (PST), jleslie48 wrote: > I think the next step is > to update the goto functionality to be a goto LABEL instead of > a PC location. So I think a good project is to add the > 'OP_LABEL [char]' mnemonic and re-tool the goto to > walk through the ROM?? looking for the label. Or, maybe, scan the ROM just once at startup, cacheing the label addresses in a


Xilinx EDK - Unable to initialize BRAM in Simulation

Started by swamy in comp.arch.fpga17 years ago 5 replies

I am getting the following error message while building a simple system consisting of bram, ppc, uart, plb bus, opb bus, plb2opb bridge. I am...

I am getting the following error message while building a simple system consisting of bram, ppc, uart, plb bus, opb bus, plb2opb bridge. I am trying to use hardware simulation to verify my design. Any help or pointers is greatly appreciated. thanks swamy Initializing Memory... Checking ELFs associated with PPC405 instance ppc405_0 for overlap... Analyzing file hello/executable.elf....


Verify failed between adress... problem

Started by bobrics in comp.arch.fpga13 years ago

Hello, I have a simple uC/OS II system with SRAM, LEDs, switches and 2 tasks as in the original example running on DE2 board. Both...

Hello, I have a simple uC/OS II system with SRAM, LEDs, switches and 2 tasks as in the original example running on DE2 board. Both tasks successfully print the message to JTAG UART when the .sop file is generated with subscription version of the tools. However, when I regenerated it with Web edition, I started getting the following error: Verifying 00080000 ( 0%) Verify failed between ...


UART RS232 "hello world" really taking shape now.

Started by jleslie48 in comp.arch.fpga13 years ago 6 replies

Just to bring those up to date, with a lot of Help from the folks here (JB, RC thank you! the project is taking some shape now. Jonathan...

Just to bring those up to date, with a lot of Help from the folks here (JB, RC thank you! the project is taking some shape now. Jonathan Bromley's I/O model is really a good point for the infamous "hello world" program that I have been trying to find. The Output model has been expanded to this now: JSEB_DATA_GENERATOR: entity work.data_gen generic map ( PC_bits => 9


Question about generic usage?

Started by fl in comp.arch.fpga15 years ago 1 reply

Hi, I am learning VHDL from Mike's example Uart.vhd in ISE 8.2. For behavioral simulation, I can run Modelsim smoothly. But for...

Hi, I am learning VHDL from Mike's example Uart.vhd in ISE 8.2. For behavioral simulation, I can run Modelsim smoothly. But for other simulation, such as post-translate or post-route simulation, there are the following warnings: # Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # do {test_uart.ndo} # ** Warning: (vlib-34) Library already exists at "work". # Model Technology ModelSim XE...


Xilinx ise ml402 bram interface

Started by Brad Smallridge in comp.arch.fpga15 years ago

I would like to be able to send and receive data on the fly to a Xilinx V4 BRAM. I would communicate to the A port while the design under test...

I would like to be able to send and receive data on the fly to a Xilinx V4 BRAM. I would communicate to the A port while the design under test would use the B port. (Or the other way around is OK to). A minimum of hardware would be nice. On this dev board there is an RS232 UART port, a USB2 port that goes through the Cypress part, an Ethernet port, the JTAG port, all of which seem to be ...