NIOS II + USB 2.0 host

Started by Anonymous in comp.arch.fpga12 years ago 6 replies

Hi, We will soon be using the Nios II as embedded controller and we would like to add a High Speed (HS) USB 2.0 hosting feature that is...

Hi, We will soon be using the Nios II as embedded controller and we would like to add a High Speed (HS) USB 2.0 hosting feature that is capable or providing a sustained transfer rate of 20 MBytes/sec. to an external HS USB 2.0 device. I realize that there are a limited number of HS USB 2.0 hosts devices/IP cores currently available. The Phillips ISP1761 is the only HS USB 2.0 component...


I/O mode to use for USB ..?

Started by Anonymous in comp.arch.fpga10 years ago 7 replies

Which I/O mode like LVDS_25 etc.. is suitable to interface USB on a Spartan-3 FPGA ..? (I know the single ended signaling within USB). The...

Which I/O mode like LVDS_25 etc.. is suitable to interface USB on a Spartan-3 FPGA ..? (I know the single ended signaling within USB). The idea being to eliminate any external usb transceiver.


xilinx impact : usb failure

Started by Anonymous in comp.arch.fpga11 years ago

Hi groups, I got a spartan3E starter kit and have experienced trouble with usb jtag interface. While using Impact, usb cable can connect...

Hi groups, I got a spartan3E starter kit and have experienced trouble with usb jtag interface. While using Impact, usb cable can connect with my laptop, but not on my desktop pc. However pc usb port/controler seems ok : there are other devices connected : wireless lan, external HD and CD/DVD recorder checked numerous cables... any clues, regards Connecting to cable (Usb Po...


Maxim anounce MAX3421E SPI-USB Host/Peri

Started by Jim Granville in comp.arch.fpga12 years ago 4 replies
USB

For those looking at smaller FPGA and USB, this new device has both Host and Peripheral modes, and has a 26MHz SPI link. Interface is via 32...

For those looking at smaller FPGA and USB, this new device has both Host and Peripheral modes, and has a 26MHz SPI link. Interface is via 32 registers, includes 15KV ESD USB drivers. Opens up FPGA access USB Flash drives as storage, and USB keyboards etc... -jg


xup-v2p: Only USB 1.1

Started by Anonymous in comp.arch.fpga10 years ago 1 reply

Hello, I'm working with a new xup rev. 04 board: Whenever I connect the integrated USB Platform cable I only get USB full speed (1.1)...

Hello, I'm working with a new xup rev. 04 board: Whenever I connect the integrated USB Platform cable I only get USB full speed (1.1) although I need the faster USB 2.0 connection. I tried 4 different machines, 3 different operating systems (VIsta, WinXP SP2, Ubuntu) even switched the USB A-B cable -- various combinations tried. The XUP board connects with 1.1, while in each and every c...


USB and AHB

Started by terabits in comp.arch.fpga11 years ago 7 replies

Hi I am very new to usb, I have some basic questions reagarding usb with ahb . Suppose i have a ahb structure like 2 masters and 2...

Hi I am very new to usb, I have some basic questions reagarding usb with ahb . Suppose i have a ahb structure like 2 masters and 2 slaves. i want to have 2usb devices .....will this usb (usb 2.0 device) sit on the slave side ? what will be on the master side ? suppose one dma as a master i have will the another master be arm processor or can it be some other usb device ? if so what cou...


USB PHY

Started by Anonymous in comp.arch.fpga9 years ago 6 replies

Hi, While searching for USB IP resources on the net I came across USB PHY cores in verilog. 1) Why is it neessary to seperate USB...

Hi, While searching for USB IP resources on the net I came across USB PHY cores in verilog. 1) Why is it neessary to seperate USB controller and PHY in two different cores? It may be necessary for 3.0 due to higher speeds but what is the need for 1.1 and 2.0? 2) If USB PHY is a mixed (Analog & Digital) solution how can it be offered only in verilog as developer claims? How can a mixe...


Parallel Cable IV does not work with parallel to usb cable

Started by Marco T. in comp.arch.fpga12 years ago 12 replies

Hallo, I bought recently a notebook with only usb, firewire, ethernet and 1 pcmcia connectors. I use Parallel Cable IV. I have bought a ps/2...

Hallo, I bought recently a notebook with only usb, firewire, ethernet and 1 pcmcia connectors. I use Parallel Cable IV. I have bought a ps/2 to usb and a parallel to usb cables. But parallel to usb seems to function only with parallel printers. Do you know a all-in-one port replicator with usb, serial and ps/2 connectors that works with Parallel Cable IV? Many Thanks Marco ...


ml-403 and USB

Started by Anonymous in comp.arch.fpga12 years ago 1 reply

Has anyone used USB from linux on the ml-403 board? I'd like to get some peripherals like usb memory or bluetooth adapter to work on it but usb...

Has anyone used USB from linux on the ml-403 board? I'd like to get some peripherals like usb memory or bluetooth adapter to work on it but usb is not in the kernel they provide. The hardware does appear to be on the board though. Thanks, Clark


USB basic doubts

Started by Datha in comp.arch.fpga14 years ago 2 replies
USB

Can somebody help me in understanding few USB related queries? What is USB host controller? What is USB device controller? What is USB OTG...

Can somebody help me in understanding few USB related queries? What is USB host controller? What is USB device controller? What is USB OTG controller? What are the different siuations which will make USB to generate interrupt? What are 'End points'? What is the meaning of 'OTG tranceiver in bi-directional mode'? What is the meaning of 'Non-OTG tranceiver in uni-directional mode'? ...


linux and USB JTAG at Spartan 3e starter

Started by Olaf in comp.arch.fpga10 years ago 4 replies

Hi, I have here my brand new Spartan 3e starter kit, therefore I could test my vhdl code in real, could ... Anyway, I'm using ISE 9.1 Sp3...

Hi, I have here my brand new Spartan 3e starter kit, therefore I could test my vhdl code in real, could ... Anyway, I'm using ISE 9.1 Sp3 Webpack for Linux and usr-driver.so from http://www.rmdir.de/~michael/xilinx. As mentioned in the README udev is configured right. Plugging the USB got in /var/log/dmesg: usb 4-5.4: new high speed USB device using ehci_hcd and address 4 usb 4-5....


Using an FPGA as USB HOST without PHY

Started by bm in comp.arch.fpga11 years ago 21 replies
USB

Hi everybody, Isi it possible to connect directly FPGA ouptuts to USB line like this : http://osainto.free.fr/USBHOST/usbDirect.pdf (Pull downs...

Hi everybody, Isi it possible to connect directly FPGA ouptuts to USB line like this : http://osainto.free.fr/USBHOST/usbDirect.pdf (Pull downs are necessary to be able to act as USB Host.) And then to use a dedicated IP for USB host role (some on opencores ) Thanks


USB Host

Started by Martin in comp.arch.fpga13 years ago 8 replies
USB

Anyone know of a device that makes implementing USB Host mode as painless as something like the FTDI chips? I need to hang a couple of USB Host...

Anyone know of a device that makes implementing USB Host mode as painless as something like the FTDI chips? I need to hang a couple of USB Host ports on a V2P. No, I don't want to implement the USB functionality within the FPGA, those logic resources are far too valuable. Ideally, I'd like a simple single-chip solution that requires almost zero work to get up and going. I do contro...


FPGA board for USB experiments?

Started by Dave Farrance in comp.arch.fpga11 years ago 26 replies

Hi. I want to get my brain around USB interfaces, how to design the hardware and the software, and eventually to find what economic hardware...

Hi. I want to get my brain around USB interfaces, how to design the hardware and the software, and eventually to find what economic hardware solutions are available, and how USB hardware interfaces can be arranged to make the best use of generic USB drivers to minimise problems associated with driver installation. It's not something that I've been able to investigate in the time-limited pr...


Virtex5 FPGA Board and USB interface

Started by XSterna in comp.arch.fpga9 years ago 5 replies
USB

Dear all, I am working on a project where I need to store datas on the Flash memory of my FPGA board. I would like to do it with the USB...

Dear all, I am working on a project where I need to store datas on the Flash memory of my FPGA board. I would like to do it with the USB interface but it is much more complicated than I could thought. I don't have any experience on USB management but in my "dream" I would like to be able to connect an USB flash drive to the FPGA, and be able to then copy 2 files on the usb flash drive to...


USB hangs on the Xilinx USB II Cable

Started by General Schvantzkoph in comp.arch.fpga6 years ago 2 replies

The Xilinx USB II cable hangs on a regular basis. I've found that pulling the USB connector out and putting it back in isn't sufficient, the...

The Xilinx USB II cable hangs on a regular basis. I've found that pulling the USB connector out and putting it back in isn't sufficient, the only way that I can get Chipscope to see it again is to power cycle the machine. I'm running SL6.1 (RHEL 6.1). The udev rules are, # version 0003 ATTR{idVendor}=="03fd", ATTR{idProduct}=="0008", MODE="666" SUBSYSTEM=="usb", ACTION=="add", ATTR{idVe...


fastest possible USB

Started by colin in comp.arch.fpga12 years ago 9 replies

Hi Does anyone have some advice for the fastest say to get many MBytes of data from a Spartan3 fifo to the hard disk of a PC via usb. I...

Hi Does anyone have some advice for the fastest say to get many MBytes of data from a Spartan3 fifo to the hard disk of a PC via usb. I assume that it is a combination of the best USB interface next to the FPGA and perhaps a USB chipset in the PC that can do some very clever DMA. I don't want to mess with custom RAID stuff I just want to dump it to a standard hard disk & controller. Any...


FPGA Internal or external USB PHY/SIE ??

Started by SJA in comp.arch.fpga2 years ago 21 replies
USB

We need to interface 8 to 16 embedded USB 2.0 devices to an FPGA. We could just use external ULPI transceivers but am wondering what FPGAs...

We need to interface 8 to 16 embedded USB 2.0 devices to an FPGA. We could just use external ULPI transceivers but am wondering what FPGAs have transceivers that are USB 2.0 compatible and if the internal USB SIE gate count is low enough to make it cost effective to wire the USB devices directly to the FPGA. (Would save lots of pins ....) Any suggestions ?


Avnet Virtex-4 LX Evaluation Kit USB FX2 Issue

Started by Anonymous in comp.arch.fpga11 years ago 2 replies

Hello, I have recently bought a Virtex-4 LX25 evaluation board from Avnet. It has Cypress FX2 chip for USB 2.0 communication support. The...

Hello, I have recently bought a Virtex-4 LX25 evaluation board from Avnet. It has Cypress FX2 chip for USB 2.0 communication support. The generic USB driver provided by Cypress is of no use to me. Whenever I connect the USB of the board with the PC, the immediate message is "Unknown USB device". This happens because the VID and PID of the device received at the host is 0. I have tried in...


The USB FPGA?

Started by Theo Markettos in comp.arch.fpga4 years ago 17 replies

I've been pondering... When it comes to attaching an FPGA to a PC, there are lots of options. First there's JTAG, then there's RS232, then...

I've been pondering... When it comes to attaching an FPGA to a PC, there are lots of options. First there's JTAG, then there's RS232, then there's ethernet, and PCIe. But there's an elephant in this room: why is USB on FPGA so hard? Sure, every FPGA can be connected to a PC with USB, but it's usually through a dumb bridge chip that does RS232, or maybe uses USB to bitbang JTAG. USB2 i...