using XIlinx impact in batch mode to generate EEPROM files

Started by Anonymous in comp.arch.fpga10 years ago 4 replies

I am using xilinx tools in an unix system to do the P&R and generate the bit file. I am using a batch mode script to go through the...

I am using xilinx tools in an unix system to do the P&R and generate the bit file. I am using a batch mode script to go through the steps. Currently I am running impact in gui mode ( either from UNIX or Windows) to generate the MCS files for the EEPROMs. Is there any way to run the impact in batch mode in UNIX to generate the MCS files? I was not able to get the information lookig at the ...


URGENT: Need to get the USB Balster Driver for the UNIX machines which has FT245BM

Started by TigerSatish in comp.arch.fpga11 years ago 3 replies

Dears Altera provided USB Balster has no driver for Unix/HP-UX The current USB Blaster provided by ALTERA uses FTDI Chip (FT245BM) to have...

Dears Altera provided USB Balster has no driver for Unix/HP-UX The current USB Blaster provided by ALTERA uses FTDI Chip (FT245BM) to have USB Interface. It uses the USB driver provided by FTDI to perform the Kit programming. That means if you want to use the USB Blaster to program a Kit using a system with UNIX Solaris platform, you need to have FTDI (FT245BM) driver for this platform (U...


EDA apps on Mac OSX?

Started by Phil Tomson in comp.arch.fpga13 years ago

OSX is basically FreeBSD unix under the hood with a very nice GUI. Given the fact that dual processor G5's are essentially high performance...

OSX is basically FreeBSD unix under the hood with a very nice GUI. Given the fact that dual processor G5's are essentially high performance Unix workstations that also happen to run all of those so-called 'productivity apps', I'm wondering if we'll see any Commercial EDA apps released for the platform? Most of the OpenSource EDA tools like Icarus, GHDL, GTKWave, etc. are already runni...


Unix workstation runs ISE 6.1 slower than a PC?

Started by Kelv...@ SG in comp.arch.fpga13 years ago 2 replies

Hi, there: I don't understand why a big chunk Sun workstation runs ISE 6 much slower than a P3-1GHz!!! Is this the right behavior or my...

Hi, there: I don't understand why a big chunk Sun workstation runs ISE 6 much slower than a P3-1GHz!!! Is this the right behavior or my workstation is lousy? I remembered my Sun was bought 2 years ago, over 10K US$... Anybody use ISE on Unix? Thanks for your reply... Kelvin


Where can i get "Quartus II Device Information for UNIX & Linux CD"

Started by Anonymous in comp.arch.fpga11 years ago 2 replies

Hi, I am tring to install Altera Quartus II v6.0 under Debian 3.1. During the install process, the install script ask me to insert the...

Hi, I am tring to install Altera Quartus II v6.0 under Debian 3.1. During the install process, the install script ask me to insert the CD: Quartus II Device Information for UNIX & Linux CD, but I searched within the www.alter.com, I cannot find it. Does anyone here has got the CD? thanks.


How to control the running of NC-Sim and Xilinx ISE under Unix?

Started by uvbaz in comp.arch.fpga11 years ago 6 replies

hi, everyone, I want to run ncvlog ncvhdl ncelab ncsim xst ngdbuild ..... under Unix. I've write a script for this, but with no...

hi, everyone, I want to run ncvlog ncvhdl ncelab ncsim xst ngdbuild ..... under Unix. I've write a script for this, but with no control statement. How can i control the running flow, namely: if (NCVLOG ERROR) then ERROR REPORT and STOP THE RUNNING.... or if (XST ERROR) then ERROR REPORT and STOP THE RUNNING.... Thanks, Cheng


ise 8.2 partitions

Started by antonio bergnoli in comp.arch.fpga11 years ago 1 reply

does anybody uses partitions in Xilinx tools by command line? It seem they are available only in project navigator or in tcl environment. I...

does anybody uses partitions in Xilinx tools by command line? It seem they are available only in project navigator or in tcl environment. I ask if it is possible to use them in a UNIX command line like bash. Thank you


What CPU for Quartus II?

Started by Anonymous in comp.arch.fpga14 years ago 1 reply

Hi all, I wonder if anyone has benchmarked contemporary high-end desktop processors -- Athlon, Opteron and P4/Xeon basically -- for which...

Hi all, I wonder if anyone has benchmarked contemporary high-end desktop processors -- Athlon, Opteron and P4/Xeon basically -- for which is better to do Quartus II synthesis? -hpa -- at work, in private! If you send me mail in HTML format I will assume it's spam. "Unix gives you enough rope to shoot yourself in the foot." Architectures needed:


[ALTERA] NIOS-II + MMU + FPU

Started by Markus Meng in comp.arch.fpga13 years ago 5 replies

Hi all, I just wonder if someone in the US could comit the following: ALTERA will bring out an update for its SOPC set featuring the MMU...

Hi all, I just wonder if someone in the US could comit the following: ALTERA will bring out an update for its SOPC set featuring the MMU and optional a FPU for the NIOS-II system. These enhancements shall be availabel this year? This would make it possible to run standard unix like Linux (MMU required) ... Best Regards Markus


VHDL syntheses timestamp

Started by Arne Pagel in comp.arch.fpga5 years ago 19 replies

Hello all, I want to implement a "build" timestamp into some FPGA Designs (like the C __DATE__ makro). Optimal would be someting like the...

Hello all, I want to implement a "build" timestamp into some FPGA Designs (like the C __DATE__ makro). Optimal would be someting like the 32Bit unix timestamp. Does anybody know if there is some method to generate a timestamp during the "syntheses time" within vhdl? Target system is xilinx spartan3 / xilinx web pack regards Arne


Gigabit Ethernet UDP/IP

Started by Klaus Falser in comp.arch.fpga11 years ago 5 replies

Hello, for a printing application I would like to receive data from a Unix workstation over Gigabit Ethernet (copper) at maximum speed. A...

Hello, for a printing application I would like to receive data from a Unix workstation over Gigabit Ethernet (copper) at maximum speed. A first test showed us that today 2 workstations are able to interchange data over GB Ethernet with about 110 MB/s, nearly at the theoretical limits. The receiver should be implemented with an FPGA, put the data into DDR memory and process the data wi...


VHDL programmer position available in Northern NJ-- westwood, NJ

Started by jleslie48 in comp.arch.fpga8 years ago

DHPC, a leader in military sensor technology development, has openings for experienced software/hardware developers in several applications. The...

DHPC, a leader in military sensor technology development, has openings for experienced software/hardware developers in several applications. The ideal candidate will have 3+ years experience in systems level programming using VHDL and FPGA in a DSP environment, using the ISE Project Navigator environment on Xilinx Virtex chipset. Programming with C/C++ using Code Composer, UNIX, Dos, and Wi...


*RANT* Ridiculous EDA software "user license agreements"?

Started by license_rant_master in comp.arch.fpga13 years ago 40 replies

I am an ASIC engineer who frequently 'takes work home' with me. Recently, I began using ssh to remotely login to our company's servers to run...

I am an ASIC engineer who frequently 'takes work home' with me. Recently, I began using ssh to remotely login to our company's servers to run some Verilog/VHDL simulations. Launching sims (from the UNIX command line) is fairly easy and painless, but any kind of interactive (GUI) operations are pitifully slow over an WAN/internet connection. In the past, I haven't needed to do much more tha...


Historical Fpga Resources

Started by Anonymous in comp.arch.fpga11 years ago 6 replies

What historical resources do we have for preserving early FPGA development? What web sites and peoples blogs are archiving this...

What historical resources do we have for preserving early FPGA development? What web sites and peoples blogs are archiving this information? Prior generations left a rich legacy of paper records, but so much of the early digital generation is being lost. We were lucky to get early Unix sources archived in the public domain. What should be we tring to get released and archived to preserve...


Xilinx UNISIM/SIMPRIM libraries

Started by Digi Suji in comp.arch.fpga9 years ago 3 replies

Hi, I am trying to do post-translate simulation on Xilinx ISE 10.1 on a PC (Win XP). When I try to compile the UNISIM/SIMPRIM libraries,...

Hi, I am trying to do post-translate simulation on Xilinx ISE 10.1 on a PC (Win XP). When I try to compile the UNISIM/SIMPRIM libraries, the system asks for 3rd party simulators. So I installed Model Sim PE student edition. I am again stuck because my design is bigger than ModelSim Student Edition would handle. My school has NC-Verilog on UNIX machines. Is there any way that I can compi...


Suggestion for Xilinx parallel port cable replacement.

Started by T Lee in comp.arch.fpga13 years ago 9 replies

How about creating a ethernet to jtag cable replacement? In that case, you only need to write a user mode program to tunnel (forward) info...

How about creating a ethernet to jtag cable replacement? In that case, you only need to write a user mode program to tunnel (forward) info from network JTAG. It will make the xmd, xst, etc on both windows and Unix platform much easier to develop, maintain and use. TCP/UDP Socket programming is so much easier to develop nad debug for all the platform. Right now, I have to build


Conversion of NCD files from 5.X to 6.1X, problem.

Started by Kelv...@ SG in comp.arch.fpga14 years ago

This is a multi-part message in MIME format. ------=_NextPart_000_0011_01C3D525.8F5E6420 Content-Type:...

This is a multi-part message in MIME format. ------=_NextPart_000_0011_01C3D525.8F5E6420 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Hi, there:=20 How do I fix this problem? I am running=20 xilperl guideconv.pl -gm leverage -par calctop.ncd calctop.ngd = calctop_61.ncd=20 It seems the xilperl uses some unix format while I am using PC...


NIOS2 1.1 toolchain sources...

Started by Jedi in comp.arch.fpga12 years ago

Has anybody the gcc/binutils sources delivered with the Linux version of NIOS2 1.1? I have a ticket open with Altera since February 4th and...

Has anybody the gcc/binutils sources delivered with the Linux version of NIOS2 1.1? I have a ticket open with Altera since February 4th and they are just stuck with the compiler rebuild problem on UNIX hosts when I use the toolchain sources from my NIOS2 Windows version. Also never got any feedback why they removed the gcc/binutils sources from their ftp with the "doc" user login men...


How to comm with Altera JTAG UART (from custom host software)?

Started by Kolja Waschk in comp.arch.fpga11 years ago 2 replies

Hi, is there any way to communicate with software running on a NIOS2 SOPC through JTAG from custom software on a Host PC? maybe via JTAG UART...

Hi, is there any way to communicate with software running on a NIOS2 SOPC through JTAG from custom software on a Host PC? maybe via JTAG UART etc... Would be nice if nios2-terminal provided a method to connect to the JTAG UART from own applications through Unix or TCP sockets, or something similar. Would be perfect if there was a public specification or source code example how to access ...


Re: Getting started with VHDL and Verilog

Started by Andreas Ehliar in comp.arch.fpga9 years ago 7 replies

On 2008-05-06, jraj.thakkar@gmail.com wrote: > Hi all, > > My background is in Software Engineering C,C++,Java and Unix. I am > getting...

On 2008-05-06, jraj.thakkar@gmail.com wrote: > Hi all, > > My background is in Software Engineering C,C++,Java and Unix. I am > getting started with VHDL and Verilog. What is the good way/books/ > websites/training to get started? I have B.S. and M.S. in Computer > Engineering. Also, what is the learning curve in VHDL and Verilog? Have you ever taken a course in d