VHDL or Verilog?

Started by Rick C. Hodgin in comp.arch.fpga4 years ago 20 replies

I've been given conflicting device on which language to use. There are people I would consider to be expert professionals who tell me to use...

I've been given conflicting device on which language to use. There are people I would consider to be expert professionals who tell me to use VHDL, and others who tell me Verilog. Most everybody tells me that if I use VHDL there's less chance for error, but that it does take more effort to learn. Any thoughts? Thank you, Rick C. Hodgin


VHDL Packages, Coding Styles for Arithmetic Operations and VHDL-200x Additions

Started by Amal in comp.arch.fpga12 years ago

Here is a presentation I did a while ago summarizing the VHDL packages, arithmetic , coding styles and the new features of VHDL-200x. ...

Here is a presentation I did a while ago summarizing the VHDL packages, arithmetic , coding styles and the new features of VHDL-200x. http://www.slideshare.net/akhailtash/vhdl-arithmetic-presentation/ Enjoy, -- Amal


Graphical VHDL Viewer ?

Started by in comp.arch.fpga13 years ago 9 replies

Hi all, Does anyone know a free/simple software that would use vhdl files to produce a graphical view ? The goal is to have a easier and...

Hi all, Does anyone know a free/simple software that would use vhdl files to produce a graphical view ? The goal is to have a easier and faster read of the architecture of a vhdl file and its components. Thanks. St?phane.


Professional VHDL Examples?

Started by Anonymous in comp.arch.fpga7 years ago 8 replies

Over the years I have taught myself Verilog and VHDL, and although I am qui= te comfortable with Verilog, I feel as though my VHDL designs are...

Over the years I have taught myself Verilog and VHDL, and although I am qui= te comfortable with Verilog, I feel as though my VHDL designs are just not = as tight as they should be. In pursuit of self-improvement, I am trying to= find "real world" examples of professional VHDL designs that I can glean f= or hints on how to make my designs better. I have read many, many books and= analyzed ...


Verilog module in VHDL project - ISE 13

Started by Mike Harrison in comp.arch.fpga9 years ago 1 reply

I want to use the Xilinx Spartan-6 XAPP495 HDMI/DVI transmit/receive modules, which are written in Verilog, in a new VHDL project, as I'm much...

I want to use the Xilinx Spartan-6 XAPP495 HDMI/DVI transmit/receive modules, which are written in Verilog, in a new VHDL project, as I'm much more familiar with VHDL - I don't do enough FPGA stuff to justify the time to learn a new language for one project. Can anyone point me towards how I can include the verilog modules and make the signals visible to my VHDL - any example of a verilog ...


Handel-C to VHDL

Started by Ahmed Ablak in comp.arch.fpga6 years ago 6 replies

When I generate VHDL from Handel-C. I always end up with an empty VHDL file, did any one face this problem? and how to solve it? Thanks

When I generate VHDL from Handel-C. I always end up with an empty VHDL file, did any one face this problem? and how to solve it? Thanks


Good VHDL reference?

Started by Nico Coesel in comp.arch.fpga13 years ago 7 replies

It seems I have misplaced my VHDL book a long time ago and I can't figure out where I left it. In short: I need a new VHDL book :-( Can anyone...

It seems I have misplaced my VHDL book a long time ago and I can't figure out where I left it. In short: I need a new VHDL book :-( Can anyone recommend a good generic VHDL reference? I'm not looking for a book with a particular bias towards fpga design, asic design, or simulation. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nl


Verilog and VHDL mix

Started by Remis Norvilis in comp.arch.fpga17 years ago 4 replies

I wonder if it is possible to synthesize on one chip VHDL and Verilog IP cores. I suppose the VHDL to Verilog or vice versa translator could...

I wonder if it is possible to synthesize on one chip VHDL and Verilog IP cores. I suppose the VHDL to Verilog or vice versa translator could be used. Ideas are welcome. Remis -- ************************************************ To reply, remove > .spam < and > .fake <


Xilinx Floating Point C Simulation aka VHDL/Verilog --> C Conversion?

Started by Simon Heinzle in comp.arch.fpga15 years ago 8 replies

Hi Guys, I need a C Simulation of some Floating Point Cores from the Xilinx coregen. I thought about automatically converting the behavioral...

Hi Guys, I need a C Simulation of some Floating Point Cores from the Xilinx coregen. I thought about automatically converting the behavioral VHDL code to C, e.g. with V2C or VHDL-2-C (found via comp.lang.vhdl FAQ part 3). While I'm investigating this -- has anyone in this group already done something similar, or are there C Simulations of the cores available somewhere? Thanks, Si...


Port mapping a Verilog component in a VHDL design

Started by ALuPin in comp.arch.fpga17 years ago 2 replies

Dear Sir or Madam, I have the following problem: I have a simulation component which is written in Verilog (not a trivial one which could...

Dear Sir or Madam, I have the following problem: I have a simulation component which is written in Verilog (not a trivial one which could be translated to VHDL). My toplevel design and all other components are written in VHDL. My question: Is it possible to include this Verilog component in my VHDL top level ? What about the types std_logic / std_logic_vector ? Can I connect the...


VHDL or Verilog

Started by Clemens Hagen in comp.arch.fpga16 years ago 6 replies

Hello I have a very basic question. Normally you have the choice if you want to use VHDL or Verilog for describing you hardware...

Hello I have a very basic question. Normally you have the choice if you want to use VHDL or Verilog for describing you hardware architecture. I would be interested when do you decide for VHDL and when for Verilog. Are the special cases when it makes more sense to use one or the other language? Thanks for helpful tips Clemens


using shared vhdl code in customer ipif block

Started by Frank van Eijkelenburg in comp.arch.fpga14 years ago 1 reply

Hi, I have a small microblaze system with my own ipif peripheral. In this peripheral I want to use a vhdl block which is also used in another...

Hi, I have a small microblaze system with my own ipif peripheral. In this peripheral I want to use a vhdl block which is also used in another part of my project. Is this possible? Because when building the system, the edk looks in the pcores/ /hdl/vhdl directory for sources (where it doesn't find the shared vhdl part and I don't want to place the shared vhdl code in this


Ambigous operator '&'

Started by Mohammed A khader in comp.arch.fpga16 years ago 3 replies

HI all, While compiling my design in Quartus II 4.2 , I got following errors. The piece of code is given below.... Error: VHDL error at...

HI all, While compiling my design in Quartus II 4.2 , I got following errors. The piece of code is given below.... Error: VHDL error at Ctrl_Ram.Vhd(66): can't determine definition of operator ""&"" -- found 2 possible definitions Error: Verilog HDL or VHDL error at Ctrl_Ram.Vhd(66): Unconverted VHDL-1402: ambiguous type: 'Regfile' or 'SIGNED' Error: VHDL Type Conversion error at Ctrl...


how to read bmp file in vhdl

Started by suni in comp.arch.fpga11 years ago 2 replies

helo i am in B.E.-E&TC,doing project on DIGITAL WATER MARKING TECH.. I need to convert matlab code in to vhdl for downloading,if not then...

helo i am in B.E.-E&TC,doing project on DIGITAL WATER MARKING TECH.. I need to convert matlab code in to vhdl for downloading,if not then how to read bmp file in vhdl?..Can u please help me out..


VHDL vs Verilog

Started by whygee in comp.arch.fpga11 years ago 38 replies

hi, recently I read a quote about VHDL vs Verilog, along the lines of "VHDL is made by SW people who don't understand HW and vice...

hi, recently I read a quote about VHDL vs Verilog, along the lines of "VHDL is made by SW people who don't understand HW and vice versa"... Does anybody know the exact wording and origin ? yg -- http://ygdes.com / http://yasep.org


How to convert Verilog in to VHDL code

Started by solomon Alemu in comp.arch.fpga11 years ago 2 replies

I have tried to convert the following verilog code manually in to VHDL in order to use it in my project which is written in vhdl. But I am...

I have tried to convert the following verilog code manually in to VHDL in order to use it in my project which is written in vhdl. But I am not able to get the same RTL results. Would you help me in converting the next module or tell me how to instantiate vhdl into verilog please? thanks in advance =======Verilog code========= `timescale 1ns / 1ps module ac97 (ready, command_addr...


VHDL model for Micron SDRAM simulation ?

Started by sjulhes in comp.arch.fpga15 years ago 6 replies

Hello all, I'm desigining a Xilinx FPGA with a sdram controller for a MT48LC8M16A2-75 memory but I can not find anymore the VHDL model on the...

Hello all, I'm desigining a Xilinx FPGA with a sdram controller for a MT48LC8M16A2-75 memory but I can not find anymore the VHDL model on the Micron's website ! Does someone know if it still possible to get a VHDL from Micron ? As there still verilog models on the Micron's website and as my modelsim simulator can handle both vhdl and verilog, can someone give some clues to use this ...


micron Flash controller VHDL disappeared ??

Started by Antti in comp.arch.fpga15 years ago 1 reply

Hi Xilinx XCELL (First Quarter 2006) has an articel that says that the VHDL code is available from Micron...

Hi Xilinx XCELL (First Quarter 2006) has an articel that says that the VHDL code is available from Micron website http://www.xilinx.com/publications/xcellonline/xcell_56/xc_pdf/p062-063_56-nand.pdf similarly microns TN2905.PDF says also that the VHDL code is available, but all the links at micron website are dead :( anyone fetched the VHDL before the links died? please contact me (i...


macro

Started by molka in comp.arch.fpga9 years ago 2 replies

Hello everybody, I need help in dealling with hard macros (in vhdl). I want to instantiate my macro in a vhdl design. any one have an idea...

Hello everybody, I need help in dealling with hard macros (in vhdl). I want to instantiate my macro in a vhdl design. any one have an idea how to do it ? I tied to do as instantiating vhdl modules but the synthesizer does not recognize my macro. Plz help. thanks in advance. ------------------------- --Mlle Molka BEN ROMDHANE --Doctorante Comelec --Bureau : DA610 --e-mail: benr...


IEEE fixed-point package FATAL_ERROR

Started by Manny in comp.arch.fpga14 years ago

Hello, Just started recently playing with a VHDL-1993 compatible...

Hello, Just started recently playing with a VHDL-1993 compatible fixed-point package: http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/files.html After introducing minor modifications to the package, it compiled on Xilinx ISE 8.1 sp3. However, now no matter how I use the function "resize" in my code, I keep on getting this message: FATAL_ERROR:Xst:Portability/export/Port_Main.h:127...