Matlab (.m) to VHDL

Started by Vitaliy in comp.arch.fpga14 years ago 3 replies

Hello, I have seen this question many times in the newsgroups but I did not see a clear answer. I have to perform various operations on...

Hello, I have seen this question many times in the newsgroups but I did not see a clear answer. I have to perform various operations on arrays of data (such as multiplication, addition, finding mean, etc.). I have code written in Matlab and would like to translate it to vhdl. I understand that such subroutines as imagesc, imwrite, etc. might not be possible to translate to vhdl and will n...


Book recommendation

Started by Paulo Ricardo Pabst in comp.arch.fpga7 years ago 11 replies

Hi, I'm new on this group. I'm starting my final year's project and I'm building a "interpolated multi-axis controller" (aka NC...

Hi, I'm new on this group. I'm starting my final year's project and I'm building a "interpolated multi-axis controller" (aka NC controller). I will use a FPGA (probably an spartan 3) to build a DDS, a quadrature encoder interface and some others digital circuits. My knowledge about VHDL is not really good, I'd read some tutorials about VHDL and I played with VHDL a little. But what I don'...


could use some help with verilog/vhdl

Started by Dan K in comp.arch.fpga13 years ago 2 replies

I'm having a problem with a state machine written in verilog that I need to get into vhdl. My simulation license only allows vhdl and I can't...

I'm having a problem with a state machine written in verilog that I need to get into vhdl. My simulation license only allows vhdl and I can't afford one that will do both. The problems is worse because it simulates just fine, but fails Xilinx ppr. But it has also run Xilinx ppr, so I'm thinking it involves the work directory and "cleanup project files" too. Perhaps if I ppr using the...


Question about lib manual of Xilinx

Started by fl in comp.arch.fpga14 years ago

Hi, The following is the VHDL example on page 699, Libraries Guide, ISE 8.1i. I have two questions in this example. 1. This example is not for...

Hi, The following is the VHDL example on page 699, Libraries Guide, ISE 8.1i. I have two questions in this example. 1. This example is not for XST (In ISE, I can use the end port map and include Library UNISIM; use UNISIM.vcomponents.all; as provided in VHDL template). Just for VHDL grammar, I am curious about INIT is defined a 8 bit bit_vector, then it declares attribute INIT : string...


Verilog, VHDL, sync and async resets

Started by johnp in comp.arch.fpga10 years ago 1 reply

We need to code some modules in both VHDL and Verilog and would like to use a parameter/generic to control inferring sync or async resets. Is...

We need to code some modules in both VHDL and Verilog and would like to use a parameter/generic to control inferring sync or async resets. Is there a clean way to code this that is similar in both VHDL and Verilog? For example, we could try to use `define in Verilog, but this won't port well to VHDL. I don't see how wen can use generate statements in Verilog to do this nicely, either. ...


Sigasi Public Beta: future of VHDL design

Started by Anonymous in comp.arch.fpga12 years ago 6 replies

Today, Sigasi proudly announces the Public Beta program for Sigasi HDT, an Intelligent Development Environment (IDE) for VHDL...

Today, Sigasi proudly announces the Public Beta program for Sigasi HDT, an Intelligent Development Environment (IDE) for VHDL (http:// www.sigasi.com/publicbeta). Sigasi HDT (Hardware Development Toolkit) is a powerful VHDL development tool that assists designers in reading, writing and modifying VHDL more accurately and faster. It differs from other development tools in that it contains a...


Need help regarding xupv2p board....

Started by Wasif Shams in comp.arch.fpga13 years ago 1 reply

I bought this board so that I can write the whole software using just VHDL. but only info i can find is... to use Power PC or microblaze core...

I bought this board so that I can write the whole software using just VHDL. but only info i can find is... to use Power PC or microblaze core using EDK and then have periphirals using VHDL. I tried to use JTAG to program the PROM to install the basic VHDL software that returns a number on hyper terminal... but it doesn't seem to work... Anybody got any idea... I would really appreciate ...


TCL SCRIPT AND VHDL DESIGN

Started by AAA in comp.arch.fpga15 years ago 2 replies

hii i have to study TCL SCRIPTING and i have to verify the VHDL codes, i have learnt this lannguage but have to verify the vhdl code using...

hii i have to study TCL SCRIPTING and i have to verify the VHDL codes, i have learnt this lannguage but have to verify the vhdl code using TCL SCRIPT. can any one out here please tell me how to go about. Any link or pdf doc. that explains how to do the same. suppose i have to verify a counter. i have to force values to teh signal, get it on the waveform. the entire process that a testbench...


ieee_ proposed library

Started by FPGA in comp.arch.fpga13 years ago 9 replies

Hello all, I am trying to use some of the proposed functions by IEEE which are still awaiting approval....

Hello all, I am trying to use some of the proposed functions by IEEE which are still awaiting approval. http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/float_pkg_c.vhdl I am getting the following errors **Error: C:/Modeltech_pe_edu_6.3c/examples/util_top.vhd(58): Library ieee_proposed not found. ** Error: C:/Modeltech_pe_edu_6.3c/examples/util_top.vhd(59): (vcom-1136) Unknown identi...


Digital Tachometer VHDL

Started by tachometer in comp.arch.fpga9 years ago 7 replies

Hi, I have this project where I have to design a tachometer using VHDL. The thing is I m pretty new to the field of electronic projects and I m...

Hi, I have this project where I have to design a tachometer using VHDL. The thing is I m pretty new to the field of electronic projects and I m very new to VHDL. The project asks me to count the Rotations/per Minute from a motor. It has to be in the range 19-98 RPM, the measurement time is 1.1s, and the display resolution is 0.1 . The good part is that I dont have to create a system to get...


where is VHDL-POSIX ?

Started by whygee in comp.arch.fpga11 years ago 4 replies

Hello, A long time ago I have heard about VHDL-POSIX. however today, when I need it, the website is...

Hello, A long time ago I have heard about VHDL-POSIX. however today, when I need it, the website is dead http://savannah.nongnu.org/projects/vhdl-posix/ and nothing can be downloaded. What has become of this project and his maintainers? Is there anything similar ? Is there an old archive where I can read the source code ? Should I rewrite all I need instead ? yg -- http://ygdes.c...


I need a good reference for VHDL

Started by Teece in comp.arch.fpga12 years ago 4 replies

Hi, I have been writing Verilog code for many years but the time has come for me to learn VHDL. Please recommend either a book or web...

Hi, I have been writing Verilog code for many years but the time has come for me to learn VHDL. Please recommend either a book or web reference or learning VHDL that would be good for someone that is experienced in FPGA architecture and Verilog. Thank You Tom tom_cip_11551@hotmail.com


Creating EDIF from Verilog, then using VHDL wrapper

Started by Robin Bruce in comp.arch.fpga15 years ago 2 replies

Hi group, here's a question: Can I synthesise a component described in Verilog, obtain an EDIF, then write a VHDL wrapper around it so as to...

Hi group, here's a question: Can I synthesise a component described in Verilog, obtain an EDIF, then write a VHDL wrapper around it so as to integrate it into a greater VHDL project. yours in ignorance, Robin


TCL testcase in Modelsim.

Started by bigyellow in comp.arch.fpga13 years ago 6 replies

Hello, Does anybody have experience on writing TCL testcase in Modelsim? I only have VHDL simulation license of Modelsim, I used to write...

Hello, Does anybody have experience on writing TCL testcase in Modelsim? I only have VHDL simulation license of Modelsim, I used to write both testbench and testcase in VHDL. But I feel VHDL is not that nice to implement testcase. So I am thinking to implement my testbench in VHDL, and write the testcases in TCL for my next project. Of course the verification should be self-checking. ...


Creating new operators

Started by rickman in comp.arch.fpga13 years ago 50 replies

In VHDL an operator can be overloaded. But can a new operator be created? There is more than once I would like to use the very...

In VHDL an operator can be overloaded. But can a new operator be created? There is more than once I would like to use the very concise notation available in Verilog such as the select operator. Is there a way to create the selection operator in VHDL? Looking at the structure, I guess it just doesn't fit the mold for VHDL with three operands. I know I can create a function for this such...


microprocessor design with vhdl

Started by VIJAY KUMAR in comp.arch.fpga9 years ago

Hello,i have knowledge of basic vhdl and i have implement a few fundemental programs on digital circuits. Iam very new to FPGA.I want to...

Hello,i have knowledge of basic vhdl and i have implement a few fundemental programs on digital circuits. Iam very new to FPGA.I want to experiment a complete details of microprocessor design with FPGA using VHDL language.starting with writing the coding.


6502 FPGA core

Started by Frank Buss in comp.arch.fpga14 years ago 17 replies

I've implemented a first version of a 6502 core. It has a very simple architecture: First the command is read and then for every command a...

I've implemented a first version of a 6502 core. It has a very simple architecture: First the command is read and then for every command a list of microcodes are executed, controlled by a state machine. To avoid the redundant VHDL typing, the VHDL code is generated with a Lisp program: http://www.frank-buss.de/vhdl/cpu.lisp This is the output: http://www.frank-buss.de/vhdl/t_rex_test.v...


VHDL code for DDFS

Started by megha in comp.arch.fpga13 years ago 7 replies

hello, i want a simple VHDL code for DDFS. its really very urgent. anyone who is having that VHDL code plz plz send me as soon as possible....

hello, i want a simple VHDL code for DDFS. its really very urgent. anyone who is having that VHDL code plz plz send me as soon as possible. thank you! my email address is roji.sweet@gmail.com


how to use the design results of the vhdl code for a program in C code

Started by lolita grenoble in comp.arch.fpga11 years ago 3 replies

hello, i need help. i work over an algo in C langage that verifies a design described in VHDL for it, i want take all informations from my...

hello, i need help. i work over an algo in C langage that verifies a design described in VHDL for it, i want take all informations from my vhdl code for use them in my programme in C and i don't know how.


VHDL and ModelSIM question

Started by Yash Bansal in comp.arch.fpga17 years ago

Hi, I have been trying to learn the "generic" statement in VHDL and as a result I have made the generic binary decoder (below) in VHDL. Note...

Hi, I have been trying to learn the "generic" statement in VHDL and as a result I have made the generic binary decoder (below) in VHDL. Note that both the encoded input A and decoded output Y are of type unsigned. Also in the "for" loop I have used "to_integer" Then I have a top level file that instantiates this decoder with SizeIn = 8 and SizeOut = 256. The design is synthesized a...