Building Gradually Expertise on VHDL/Verilog Design

Started by Anonymous in comp.arch.fpga14 years ago 3 replies

Hi, i have been reading the VHDL language over the last week and now i want to put what i have learned so far into practice but don't...

Hi, i have been reading the VHDL language over the last week and now i want to put what i have learned so far into practice but don't know really from where to start. As such, i am just wondering if there is any lab book or a web based tutorials that help a newbie like me to gradually get a grip on vhdl design techniques on FPGA. I am seeking any series of recommended labs to proceed thro...


16550 VHDL code

Started by Anonymous in comp.arch.fpga15 years ago 1 reply

Hello, I'm currently writing VHDL code for an Altera cyclone, the EP1C6. One of the modules i need is an 16550 compatible UART which has...

Hello, I'm currently writing VHDL code for an Altera cyclone, the EP1C6. One of the modules i need is an 16550 compatible UART which has to communicate through an ISA bus (PC104). My question is if somebody has the VHDL code for it, or can tell me where i can find code (i've already asked quotes at core suppliers but this is a little bit expensive). Thanks in advance


DK: Interfacing Handel C and VHDL

Started by Leow Yuan Yeow in comp.arch.fpga15 years ago

Hi, I have been trying to make an example work in the DK Design Suite but to no avail. Can anyone who has experience in DK help me? The example...

Hi, I have been trying to make an example work in the DK Design Suite but to no avail. Can anyone who has experience in DK help me? The example is listed under Celoxica\DK\Examples\VHDL\Examples2 and it is one of the example listed in the help file which teaches how to interface handel c with vhdl code. The example can be found by search "vhd" under the celoxica help. However after I compil...


c++ lcd device driver 2vp4

Started by Tom Tassignon in comp.arch.fpga17 years ago

Hi, is there anyone out there who has some experience with the lcd module of the v2p4 memec board with virtex 2 pro fpga on it ? I am trying...

Hi, is there anyone out there who has some experience with the lcd module of the v2p4 memec board with virtex 2 pro fpga on it ? I am trying to get the lcd working by writing only c++, no vhdl. I am using the opb_gpio pins to control the lcd module. I have another design where the lcd module works fine with vhdl. When I measure the voltage of the pins on the lcd module of the vhdl de...


VHDL Editors (esp. V3S)

Started by Anonymous in comp.arch.fpga4 years ago 14 replies

As X and A's integrated editors are more or less limited, I guess many people will looking for better alternatives. The usual suspects will be...

As X and A's integrated editors are more or less limited, I guess many people will looking for better alternatives. The usual suspects will be Emacs (with VHDL mode) and Sigasi. For me personally, I never really liked Emacs and found Sigasi just a bit too expensive. So some time ago I came across V3S from www.vide-software.at. It is a quite powerful and fair priced VHDL plug-in f


clock division using DCM, how?

Started by Anonymous in comp.arch.fpga16 years ago 2 replies

Hello to all of you, currently I'm working on a "game of life" implementation on FPGA. Everything seems to work fine except for some pixel...

Hello to all of you, currently I'm working on a "game of life" implementation on FPGA. Everything seems to work fine except for some pixel columns that are giving strange results. I'm quite convinced that the vhdl code, which you can find on my site ( http://jefpatat.freefronthost.com/vhdl/game%20of%20life/VHDL%20code.htm ) is correct. So I assume the error is related to timing problems o...


clock division using DCM, how?

Started by Jef Patat in comp.arch.fpga16 years ago

Hello to all of you, currently I'm working on a "game of life" implementation on FPGA. Everything seems to work fine except for some pixel...

Hello to all of you, currently I'm working on a "game of life" implementation on FPGA. Everything seems to work fine except for some pixel columns that are giving strange results. I'm quite convinced that the vhdl code, which you can find on my site ( http://jefpatat.freefronthost.com/vhdl/game%20of%20life/VHDL%20code.htm ) is correct. So I assume the error is related to timing problems ...


VHDL models for DDR2 SDRAM?

Started by Pete in comp.arch.fpga13 years ago 1 reply

Can someone please recommend some VHDL DDR2 SDRAM models? Specifically, I'm targetting a MT47H64M16 part. I've tried using an open source model...

Can someone please recommend some VHDL DDR2 SDRAM models? Specifically, I'm targetting a MT47H64M16 part. I've tried using an open source model from the "Free Model Foundry," but it's buggy and doesn't support seamless writes. Micron doesn't seem to be publishing free VHDL models anymore (only Verilog). We run a VHDL shop and don't even have Verilog/Mixed licenses for our simulator. Do...


WebPack - mixed design flow

Started by Valentin Tihomirov in comp.arch.fpga17 years ago 1 reply

My system has netlist in EDIF while some of technology elements used in the netlist are described in a separate VHDL file at logic level....

My system has netlist in EDIF while some of technology elements used in the netlist are described in a separate VHDL file at logic level. WebPack supports only pure EDIF, schematic, Verilog or VHDL design flows. Is ther a way to compile a mixed design? That is, I first elaborate VHDL and then load EDIF netlist which uses VHDL components. May be ISE Foundation supports this?


crc32 vhdl implementation (4 bit data)

Started by Moti Cohen in comp.arch.fpga17 years ago 10 replies

Hy all, I'm currently implementing a receiver (vhdl) part of the ethernet mac which is responsible for the MII interafce. I'm need an...

Hy all, I'm currently implementing a receiver (vhdl) part of the ethernet mac which is responsible for the MII interafce. I'm need an crc32 calculator (RTL) to check the FCS field. I've tried using the easics crctoll in order to create the mechanism (for a 4 bit data input) but it does not seems to work. does anyone have a working (rtl) vhdl implementation for this block? or at least a detai...


VHDL: Use of literal '1' on an input port ?

Started by Rajeev in comp.arch.fpga17 years ago 6 replies

Hello all, I'm still working with DSPBuilder. Here's a VHDL problem that I can fix but don't understand. DSPBuilder.vhd has a...

Hello all, I'm still working with DSPBuilder. Here's a VHDL problem that I can fix but don't understand. DSPBuilder.vhd has a line obj:lpm_add_sub port map (cin => '1'); Quartus is happy with this, and in fact I use constant port values in my own VHDL all the time. But Model Technology (Altera Edition 5.7e) complains: # ** Error: Actual for formal cin is not a signal.


hex rep. in VHDL

Started by anupam in comp.arch.fpga15 years ago 11 replies

hi, I have a small query in VHDL language. Like we write in Verilog fifo_data

hi, I have a small query in VHDL language. Like we write in Verilog fifo_data


builing a SPI interface in vhdl

Started by techG in comp.arch.fpga13 years ago 7 replies

HI, I'm new in FPGA, I have to build a SPI interface (in VHDL) to let an fpga read and write a flash memory. The fpga is a Xilinx Spartan3E,...

HI, I'm new in FPGA, I have to build a SPI interface (in VHDL) to let an fpga read and write a flash memory. The fpga is a Xilinx Spartan3E, while the memory is an ST M25P16 (serial I/O). Do you know if is there any built vhdl core to start with? Thanks in advance Giulio


Using both Verilog and VHDL for Xilinx simulation

Started by Michael in comp.arch.fpga9 years ago 1 reply

Hi, How do I setup synopsys_sim.setup for simulating both Verilog and VHDL using VCS for a Xilinx FPGA? I need for instance have SIMPRIM...

Hi, How do I setup synopsys_sim.setup for simulating both Verilog and VHDL using VCS for a Xilinx FPGA? I need for instance have SIMPRIM point to both the VHDL and the Verilog compiled library path, I did try using a : and simply append them but it failed. /michael


need help with vhdl code in custom IP

Started by Anonymous in comp.arch.fpga15 years ago

Hi, I'm trying to do multiply-and-accumulate (MAC) in a custom IP created by Create/Import IP peripherals in XPS. Xilinx provides...

Hi, I'm trying to do multiply-and-accumulate (MAC) in a custom IP created by Create/Import IP peripherals in XPS. Xilinx provides basic read/write functions with the user_logic vhdl code. I removed the code for reg2 and reg3 in these two processes. I then added MUL_AND_ACCUM process. I'm not a vhdl programmer, so I'm having difficulty with this simple piece of logic. All I'm trying to do is ...


Call for Participation Accellera VHDL Verification Features

Started by Jim Lewis in comp.arch.fpga14 years ago

Hi, If you have strong verification skills and have used a language such as SystemVerilog, e, Vera, or SystemC for verification and would like...

Hi, If you have strong verification skills and have used a language such as SystemVerilog, e, Vera, or SystemC for verification and would like to be able to use VHDL, you should be participating in the Accellera VHDL enhancments effort. Some of the tasks on our list are adding OO, interfaces, constrained random, functional coverage, verification data structures, ... You do not need to...


VHDL Manipulation and Generation Intrerface - vMAGIC 0.3.0 released

Started by CP in comp.arch.fpga11 years ago

The new vMAGIC release includes a number of new features, such as a new type handling system, simplified expression building, customizable VHDL...

The new vMAGIC release includes a number of new features, such as a new type handling system, simplified expression building, customizable VHDL output, and (finally) support for several things that have so far been missing (like VHDL package building). Also, the new version uses much less memory and performance was dramatically improved. This of course implies some massive changes to the API,...


FSL to VHDL interface

Started by Anonymous in comp.arch.fpga15 years ago 9 replies

Hello, I'm having great difficulty interfacing my FSL to my external (from microblaze point of view) VHDL. I want an FSL to communicate...

Hello, I'm having great difficulty interfacing my FSL to my external (from microblaze point of view) VHDL. I want an FSL to communicate between Microblaze and my external VHDL. I want to be able to import the .xmp file to my ISE project and then create the instantiation template (wrapper) for the XMP file (*_stub.vhd). In the file I need to see the FSL control signals, data etc. I cann...


Four_Bit_Counter in VHDL

Started by Marvin L in comp.arch.fpga5 years ago

I am implementing four-bit-counter but I am getting value of x for Port_co= unter in auto-counting. http://pastebin.com/z1Kh7D3J (VHDL code) and...

I am implementing four-bit-counter but I am getting value of x for Port_co= unter in auto-counting. http://pastebin.com/z1Kh7D3J (VHDL code) and http:/= /pastebin.com/2kY3hQAN (testbench). I already finished the two flip-flop in= VHDL. I am now stuck with simulation. http://i.imgur.com/WXFQC5f.png Someone told me that the usual reason for an undefined output is failure t= o initialize al...


Four_Bit_Counter in VHDL

Started by Marvin L in comp.arch.fpga5 years ago 9 replies

I am implementing four-bit-counter but I am getting value of x for Port_cou= nter in auto-counting. http://pastebin.com/z1Kh7D3J (VHDL code) and...

I am implementing four-bit-counter but I am getting value of x for Port_cou= nter in auto-counting. http://pastebin.com/z1Kh7D3J (VHDL code) and http://= pastebin.com/2kY3hQAN (testbench). I already finished the two flip-flop in = VHDL. I am now stuck with simulation. http://i.imgur.com/WXFQC5f.png Someone told me that the usual reason for an undefined output is failure to= initialize all ...