Chipscope Pro and VHDL

Started by Anonymous in comp.arch.fpga16 years ago 1 reply

I was reading the manuals for Chipscope Pro and I am a bit confused. Does ChipScope Pro generate some sort of VHDL block that you place in your...

I was reading the manuals for Chipscope Pro and I am a bit confused. Does ChipScope Pro generate some sort of VHDL block that you place in your design and connect the appropriate signals to? Or does it generate some vhdl code which you paste into a block? I am using chipscope pro 6.2i. If anyone has information in regards to this, pleas elet me know. Thanks Vivek


learning verilog

Started by kristoff in comp.arch.fpga4 years ago 7 replies

Hi all, I am currently learning VHDL step by step, but I noticed there are also quite a lot of projects written in verilog. So, for...

Hi all, I am currently learning VHDL step by step, but I noticed there are also quite a lot of projects written in verilog. So, for somebody who knows the basis, what would be best? - First get a very good knowledge of VHDL and then start with verilog - or learn vhdl and verilog at the same time (as the two languages do offer simular features). Kristoff


RS-232 Bus controller design in VHDL

Started by ikki in comp.arch.fpga12 years ago 17 replies

Hi there everyone, I hope I could find my answer here. I am looking for RS-232 bus controller design in VHDL. To be precise, I need the...

Hi there everyone, I hope I could find my answer here. I am looking for RS-232 bus controller design in VHDL. To be precise, I need the Receiver and Transmitter coding in VHDL. I will only be using 3 pins out of 9 pins of the DB9. There are RXD , TXD and ground signals. My DTE is PC while my DCE is Xilinx Spartan 3. Im planning to send data using hyperterminal from PC to RS-232 receiver...


Xilinx Spartan3 DCM Procedure

Started by Brad Smallridge in comp.arch.fpga17 years ago 1 reply

Not sure what to do here. I ran the wizard for a Single DCM which generated a XAW file. Although this is a "New Source" it doesn't act like...

Not sure what to do here. I ran the wizard for a Single DCM which generated a XAW file. Although this is a "New Source" it doesn't act like one. One can generate VHDL code from this XAW file which I did. I then tried to add the VHDL code as a source and got an error message. Something about a conflict between the two files. So I deleted the XAW file and now the VHDL file, by itself, seem...


Verilog Book for VHDL Users

Started by rickman in comp.arch.fpga10 years ago 22 replies

I am finally going to learn Verilog for real after using VHDL for 15 years. I've done a little work with Verilog and found it relatively easy...

I am finally going to learn Verilog for real after using VHDL for 15 years. I've done a little work with Verilog and found it relatively easy to use. Now I want to learn the details and especially how not to make mistakes. VHDL has the problem of not letting you do things unless you make it explicitly clear what you want to do. My understanding is that Verilog will let you not specify f...


VHDL I2c burst read

Started by Anonymous in comp.arch.fpga4 years ago 6 replies

Dear All, please help with VHDL, i connected MPU6050 to my FPGA board. I used www.eewiki.com tutorial, can anybody exlpain me how to read...

Dear All, please help with VHDL, i connected MPU6050 to my FPGA board. I used www.eewiki.com tutorial, can anybody exlpain me how to read burst data 16 bits from 2 registers or 6 regsiters ? by only one operation ? I use https://eewiki.net/pages/viewpage.action?pageId=11042934#SPItoI2CBridge(VHDL)-CodeDownload but reads only 1 byte . any suggestion would be appreciated/


Quartus help with package declaration

Started by Pratip Mukherjee in comp.arch.fpga17 years ago 1 reply

Hi, Using QuartusII 3.0, I have a VHDL file with a package declaration. From a VHDL file in a project I can see the declarations in the...

Hi, Using QuartusII 3.0, I have a VHDL file with a package declaration. From a VHDL file in a project I can see the declarations in the pacakage by using use work. .all; But from another VHDL file in the same project, the same 'use' line gives the following error: Error: VHDL Use Clause error at .vhd( ): design library work does not contain primary unit


XST Internal error: VHDL constant record support

Started by Anonymous in comp.arch.fpga15 years ago 3 replies

Hi All, Just wanted to know if anyone has experienced any problems with Xilinx XST when declaring a constant record in VHDL. Below is...

Hi All, Just wanted to know if anyone has experienced any problems with Xilinx XST when declaring a constant record in VHDL. Below is some, what I hope to be valid, VHDL, that makes XST fail and spit out a Internal Error. I'm using ISE 7.1 (SP4) running on a Linux Box. Is this really an XST bug/problem/deficiency? Would be great to hear from any 8.1 users to see if this is still a p...


AHB VHDL code

Started by praveen in comp.arch.fpga16 years ago 1 reply

Hello, 1.Can anyone provide me with some AMBA AHB VHDL models?or is there anyone who has designed one? 2. What is role played by...

Hello, 1.Can anyone provide me with some AMBA AHB VHDL models?or is there anyone who has designed one? 2. What is role played by wrapper??? Thanks and regards Praveen


Bayer Pattern to RGB VHDL CODE

Started by Anonymous in comp.arch.fpga2 years ago 1 reply

Please VHDL Guru's i got 8 rows Bayer signal from MT9 parallel data camera , could someone help me or share VHDL code to convert from Bayer...

Please VHDL Guru's i got 8 rows Bayer signal from MT9 parallel data camera , could someone help me or share VHDL code to convert from Bayer pattern to RGB ?


Sharing VHDL Verification IP

Started by Espen Tallaksen in comp.arch.fpga3 years ago

Sharing VHDL Verification Components (VVC) within the FPGA/VHDL community has previously been difficult because there was no standardised way of...

Sharing VHDL Verification Components (VVC) within the FPGA/VHDL community has previously been difficult because there was no standardised way of interfacing to and controlling these VVCs. A solution on this challenge could easily reduce the project verification time by 20 to 80%, and at the same time improve the FPGA quality. The open source UVVM has over the last two years standard


Inferring multiple-DSP48 pipelined multiplier in VHDL

Started by Robin Bruce in comp.arch.fpga15 years ago 13 replies

Hi Guys, I'm having trouble with the following problem: I'm trying to create a 35x35 signed multiplier from DSP48s, inferring pipelining in...

Hi Guys, I'm having trouble with the following problem: I'm trying to create a 35x35 signed multiplier from DSP48s, inferring pipelining in VHDL by adding registers after the multilplication operation as seen below in the VHDL I'm using. The problem is that when I synthesise, though I can see that the synthesiser has noticed that it can shift registers about: Synthesizing (advanced)...


Inferring multiple-DSP48 pipelined multiplier in VHDL

Started by Robin Bruce in comp.arch.fpga15 years ago

Hi Guys, I'm having trouble with the following problem: I'm trying to create a 35x35 signed multiplier from DSP48s, inferring pipelining in...

Hi Guys, I'm having trouble with the following problem: I'm trying to create a 35x35 signed multiplier from DSP48s, inferring pipelining in VHDL by adding registers after the multilplication operation as seen below in the VHDL I'm using. The problem is that when I synthesise, though I can see that the synthesiser has noticed that it can shift registers about: Synthesizing (advanced)...


VHDL

Started by Anonymous in comp.arch.fpga15 years ago 6 replies

Now, I used the state machine to apply to VHDL. In my case, there are two states, S0 and S1. When I press a button, S0 is transit to S1 such...

Now, I used the state machine to apply to VHDL. In my case, there are two states, S0 and S1. When I press a button, S0 is transit to S1 such that the LED display some of the segments,like segment a,b,c. And press this button again, S1 is back to S0. How can I present in VHDL so that the LED display in segment a,b,c ? Thanks!!


VHDL test bench in Quartus

Started by Pratip Mukherjee in comp.arch.fpga17 years ago 7 replies

Is it possible to write a test bench using VHDL in Quartus? When I tried I got an error message telling me that wait construct is not...

Is it possible to write a test bench using VHDL in Quartus? When I tried I got an error message telling me that wait construct is not supported. Is that true or am I making some mistake? Is there any way, may be using tcl, I can simulate a VHDL like test bench? Testbench using waveforms just does not work for me. Thanks. Pratip Mukherjee pratipm.remove_this@hotmail.com


vhdl and clock-pin

Started by in comp.arch.fpga16 years ago 2 replies

Hi, when I use a CLK input-pin in vhdl in my top-level file, is this automatically the clk signal of my device? Or do I have to constrain it...

Hi, when I use a CLK input-pin in vhdl in my top-level file, is this automatically the clk signal of my device? Or do I have to constrain it to the correct PIN? regards, Benjamin


Manually creating a LUT in VHDL

Started by David in comp.arch.fpga14 years ago 4 replies

Does anyone know if it is possible to define the values in a lookup table using VHDL compatible with Xilinx tools? If so, does anyone have an...

Does anyone know if it is possible to define the values in a lookup table using VHDL compatible with Xilinx tools? If so, does anyone have an example? Thanks, David


Re: VHDL long elsif state machine

Started by Anonymous in comp.arch.fpga12 years ago 1 reply

Beat me to the punch. I also recommend reading this paper and his others. Case statements in VHDL are automatically parallel and full...

Beat me to the punch. I also recommend reading this paper and his others. Case statements in VHDL are automatically parallel and full anyway. ---Matthew Hicks > Gabor > > > If it were Verilog I would use a case statement and > > add "// synthesis parallel-case" to remove the priority > > logic. Since this is a synthesis directive, it might > > also work in VHDL? > If your assumpt


0x80000000 Integer not supported??

Started by cdb in comp.arch.fpga10 years ago 10 replies

Hi everybody, I'm designing a VHDL testbench for a VHDL module. I have to generate values to be written into a 32 bit register of...

Hi everybody, I'm designing a VHDL testbench for a VHDL module. I have to generate values to be written into a 32 bit register of my module. I decided tu use integer variables to compose my data and than convert them to std_logic_vector to perform the write operation on the module. The issue is that I discovered that VHDL integer range is from -2147483647 to 2147483647, that is to say ...


Synthesizing VHDL delays [noob]

Started by Roland in comp.arch.fpga15 years ago 2 replies

Hi! I have a question regarding the VHDL's "after" keyword. I've read that it is not synthesizable but only used for simulation and I was...

Hi! I have a question regarding the VHDL's "after" keyword. I've read that it is not synthesizable but only used for simulation and I was wondering if this is true for real-world programs. I'm working with Xilinx Spartan-2 (so it's Xilinx's systhesizer in question) and I've connected a soft processor to an external memory chip via my VHDL memory controller but the design isn't working...