Do you prefer paper or plastic... er, I mean paper or e-books?

Started by rickman in comp.arch.fpga12 years ago 10 replies

I find there are any number of aspects of the VHDL language that I just do not remember and I am not going to make up flash cards to help me...

I find there are any number of aspects of the VHDL language that I just do not remember and I am not going to make up flash cards to help me remember. So I drag a half dozen VHDL books around with me when I am working on VHDL (or much less frequently, Verilog; one of the books covers both). I am getting tired of heaving the books up into the truck every time I go to the lake and am starti...


converting verilog to vhdl

Started by Anuja in comp.arch.fpga13 years ago 13 replies

Hello I am trying to convert the following code to vhdl assign Q = (rst==0)?Q_int:1'do; How do i convert this to vhdl? I have to use a...

Hello I am trying to convert the following code to vhdl assign Q = (rst==0)?Q_int:1'do; How do i convert this to vhdl? I have to use a concurrent statement as this statement is not in the always block hence concurrent. I cannot use an if then else statement as it is sequential. Please help


FFT in VHDL (or Verilog) Tutorial

Started by Student (confused) in comp.arch.fpga14 years ago 2 replies

Hello, Can someone point me to simple implementation of FFT in VHDL(or Verilog) with testbench and good step-by-step description. I...

Hello, Can someone point me to simple implementation of FFT in VHDL(or Verilog) with testbench and good step-by-step description. I have implementation from Xilinx (which I will eventually use for hardware implementation), but I find it rather confusing (lack of vhdl experience). Algorithm used, # of points, Radix#, bit precision do not matter, as I'm looking for tutorial-like implementati...


Free Arm Version 0.8

Started by Konrad Eisele in comp.arch.fpga17 years ago 1 reply

Open Source synthesizable Arm vhdl model: For those that are interested: We have allocated a Opencores Project...

Open Source synthesizable Arm vhdl model: For those that are interested: We have allocated a Opencores Project at: http://www.opencores.org/projects.cgi/web/core_arm/overview The source can be checked out via CVS or snapshots. Meanwhile on sourceforge you can browse them too. Vhdl files are annotated and nice to read. http://skdec.sourceforge.net/build_html/vhdl/index.htm Slowly but shur...


Questions about counter in VHDL

Started by Anonymous in comp.arch.fpga15 years ago 13 replies

I have implemented a 8-bit synchronous counter by VHDL. The result is that the LED display show continuously running the count from 0 to F(in...

I have implemented a 8-bit synchronous counter by VHDL. The result is that the LED display show continuously running the count from 0 to F(in Hex). Now, I need to change the result which the LED display can count from 0 to 9 only. How can I change in the VHDL code? Can anyone answer me? Thanks a lot!! The following VHDL code are about 8-bit synchronous counter: Library IEEE; USE IEEE.std_...


Opinion on Altium's nVisage VHDL tools?

Started by Niki Steenkamp in comp.arch.fpga17 years ago

Hi, I am looking for a reasonably priced front-end toolset for VHDL multi-vendor FPGA design. This should as a minimum provide: * VHDL...

Hi, I am looking for a reasonably priced front-end toolset for VHDL multi-vendor FPGA design. This should as a minimum provide: * VHDL design entry (text based and high level graphical) * Functional simulation (testbenches with file I/O) * Post-synthesis and timing (post-PAR) simulation. For this I am considering ActiveHDL, but since we also do a lot of hardware design using the Prote...


Where can i get free CAN VHDL core

Started by Anonymous in comp.arch.fpga14 years ago 4 replies

Hi, I am going through the net to download CAN VHDL core. HurriCANe is removed from the ESA site, and the link in opencores site for VHDL...

Hi, I am going through the net to download CAN VHDL core. HurriCANe is removed from the ESA site, and the link in opencores site for VHDL CAN core is going to some odd page. can you please guide me on where i can download this or if anyone does have these free versions can you mail me ? Thank you for your time raju


question about filter design vhdl

Started by viswanath in comp.arch.fpga17 years ago 1 reply

Hi, I have to design a low pass filter in VHDL. How can one go about designing such a filter when the medium is event driven and time domain...

Hi, I have to design a low pass filter in VHDL. How can one go about designing such a filter when the medium is event driven and time domain based?? How should one decide on the filter characteristics if we just know the symbol time rate. If I am using standard VHDL and not AMS is it possible for me to design such a filter which is used in the recovery loops of receiver? Most of the refer...


Visualizing VHDL

Started by Kevin Kilzer in comp.arch.fpga17 years ago 11 replies

When you write VHDL (or Verilog for that matter), do you visualize a schematic with wires, gates, flops, latches, muxes, etc., or do you use...

When you write VHDL (or Verilog for that matter), do you visualize a schematic with wires, gates, flops, latches, muxes, etc., or do you use some other way of thinking about it? Kevin


Good, affordable verilog simulator

Started by Paul Taddonio in comp.arch.fpga16 years ago 11 replies

Can anybody recommend a good PC-based verilog simulator for substantially less than $4500? I am a new hire at a company which spent big bucks...

Can anybody recommend a good PC-based verilog simulator for substantially less than $4500? I am a new hire at a company which spent big bucks on ModelSim just two years ago. Unfortunately we purchased VHDL and I am a verilog designer. We have a tight schedule so I will stick with the familiar language. I would use the VHDL simulator but Xilinx tools won't put out a VHDL model from verilog sourc...


Integrate VHDL Cores in Microblaze (Spartan 3E Starter Kit)

Started by Pablo in comp.arch.fpga14 years ago

Hi, I am trying to integrate a ps2 core (for Keyboard) to Microblaze with the Create/Import Wizard. I cannot get this integration since an error...

Hi, I am trying to integrate a ps2 core (for Keyboard) to Microblaze with the Create/Import Wizard. I cannot get this integration since an error occur from "Sys_clk_pin". The question is the following? How can I incorporate VHDL code to a design with MIcroblaze, because I have a Microblaze system with a program.c and a vhdl core and I want to download both to the Spartan 3E. Thanks, a...


How process statement works in vhdl

Started by ZHI in comp.arch.fpga15 years ago 2 replies

Hello, I a newer to vhdl. I am trying to change my algorithm form matlab to vhdl. I met RAMs conflict when I did...

Hello, I a newer to vhdl. I am trying to change my algorithm form matlab to vhdl. I met RAMs conflict when I did it. *********************************************************** library IEEE; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library unisim; use unisim.vcomponents.all; entity dcdtest3 is generic (Nit: integer:=20000; H: integer...


A question from a VHDL beginner

Started by ales...@gmail.com in comp.arch.fpga11 years ago 4 replies

Dear everybody, I'm a beginner in using the VHDL and I'm experiencing some problems during the testing phase. I have developped a small VHDL...

Dear everybody, I'm a beginner in using the VHDL and I'm experiencing some problems during the testing phase. I have developped a small VHDL model based on an Altera Cyclone FPGA and, using ModelSim, I have tested it in simulation mode. The results from simulation were goods, so I decided to synthesize the model and test it on the FPGA. With my surprise, the model doesn't work well as ...


Mac OS X support for Sigasi HDT

Started by Hendrik in comp.arch.fpga11 years ago 2 replies

Today, Sigasi proudly announces Mac OS X support for Sigasi HDT, an Intelligent Development Environment (IDE) for VHDL. Sigasi HDT is built...

Today, Sigasi proudly announces Mac OS X support for Sigasi HDT, an Intelligent Development Environment (IDE) for VHDL. Sigasi HDT is built upon the widely accepted Eclipse platform and contains an ultra-fast VHDL parser and compiler. As a result, the tool fully understands a design in terms of VHDL concepts. The tool is currently available in a public beta program. From user feedback, w...


Q)BRAM VHDL simulation in modelsim

Started by pasacco in comp.arch.fpga16 years ago 2 replies

Hi I have a problem in simulating a memory block (VHDL-written control unit and BlockRAM for Virtex II). BRAM is instantiated as shown...

Hi I have a problem in simulating a memory block (VHDL-written control unit and BlockRAM for Virtex II). BRAM is instantiated as shown below. The problem for me is that the VHDL description of BRAM is not available. The question is that - Can we simulate it in modelsim SE 6.0c? - In case only the BRAM-instantiation is enough to simulate and synthesize, is it meaning that simulator/synth...


VHDL: Process vs concurrent stataments?

Started by p.tucci <a t> gmail.com in comp.arch.fpga12 years ago 2 replies

Hi all, I'm a VHDL beginner and I've a trouble with a simple VHDL piece code. Writing the same thing in two ways that (appearently to me) seem...

Hi all, I'm a VHDL beginner and I've a trouble with a simple VHDL piece code. Writing the same thing in two ways that (appearently to me) seem to be the same, produce different resuls. In one case the code is synthesized, in the other it is not. This is the first piece of code, written as a process. It is well synthesized: sample_parallel_data : process(SYS_CK_IN,RESET) begin if...


Actel Designer: how to compile VHDL top & EDIF submodule together?

Started by robotron in comp.arch.fpga10 years ago 5 replies

Hello, I need to implement a measurement instrument in FPGA, where direct placement of several simple blocks (eg. DFFs) must be achieved. So...

Hello, I need to implement a measurement instrument in FPGA, where direct placement of several simple blocks (eg. DFFs) must be achieved. So I created an EDIF netlist, describing one subcircuit, and the rest (top level entity) coded in VHDL. The target architecture is Actel ProASIC3E, development suite Libero 9 & Synplify. The VHDL part has been synthesised using Synplify, producing well...


advanced vhdl lerning

Started by CMOS in comp.arch.fpga15 years ago 2 replies

hi, i've completed a introdutory vhdl book and done several small scale designs using vhdl for FPGA implementations. However the book i...

hi, i've completed a introdutory vhdl book and done several small scale designs using vhdl for FPGA implementations. However the book i read does not cover any advanced topics or designs that we meet in real life, like micro-controllers, USB interfaces, etc. i' ve serched the net for books and tutorials which will discuss advanced topics and having a moderately complex case study at the end,...


mixed Verilog/VHDL in ispLever 7.0 broken

Started by Richard Klingler in comp.arch.fpga14 years ago 2 replies

G'day (o; Just got the confirmation that ispLever 7.0 is broken for mixed Verilog/VHDL designs...my case was that a VHDL T80 Z80 CPU core...

G'day (o; Just got the confirmation that ispLever 7.0 is broken for mixed Verilog/VHDL designs...my case was that a VHDL T80 Z80 CPU core module wrapped in a Verilog top file would fail with Precision unable to find work library... Now with the patch it's running through (o; Either contact Lattice for a fix if you have this issue or wait until end of year for ispLever 7.1 (o; che...


DSP core, use of real type signals (Altera Stratix)

Started by Erik Verhagen in comp.arch.fpga15 years ago 1 reply

Hello, I have a little problem, it is about real values in VHDL, and the way = Quartus is managing them. I am describing a simple DSP function...

Hello, I have a little problem, it is about real values in VHDL, and the way = Quartus is managing them. I am describing a simple DSP function (filter) in VHDL to implement on a = Stratix device. As you probabely know, these functions need to shift = input values in a register bank (declared as "signal" in VHDL), applying = coefficients (reals) to them. These signals must therefor be of real...