Perl Preprocessor for HDL

Started by Kevin Neilson in comp.arch.fpga16 years ago 7 replies

Because of the deficiencies in Verilog or the tools, I often have to write Perl to generate Verilog. Examples of these deficiencies...

Because of the deficiencies in Verilog or the tools, I often have to write Perl to generate Verilog. Examples of these deficiencies include: - Port list is not parameterizable without use of `defines - Many synthesizers don't understand preprocessing constant functions - Generate function in Verilog has limitations Rather than write Perl to generate Verilog modules, which is a cumbers...


Thomas & Moorby Verilog Reference: $41

Started by hdl_book_seller in comp.arch.fpga14 years ago 3 replies

We're down to the last 10 copies of the popular Verilog reference book, Thomas & Moorby's classic "The Verilog Hardware Language" at only $41...

We're down to the last 10 copies of the popular Verilog reference book, Thomas & Moorby's classic "The Verilog Hardware Language" at only $41 -- over 66% off the Amazon price of $119. We have sold hundreds of these books to chip designers and students worldwide. This classic Verilog reference text is brand new and in the original plastic wrapper, WITH CDROM. We ship with free Priority ...


VHDL or Verilog

Started by Clemens Hagen in comp.arch.fpga16 years ago 6 replies

Hello I have a very basic question. Normally you have the choice if you want to use VHDL or Verilog for describing you hardware...

Hello I have a very basic question. Normally you have the choice if you want to use VHDL or Verilog for describing you hardware architecture. I would be interested when do you decide for VHDL and when for Verilog. Are the special cases when it makes more sense to use one or the other language? Thanks for helpful tips Clemens


Delays in verilog

Started by Gerr in comp.arch.fpga16 years ago 7 replies

Hi, I'm a bit confused by the do's and dont's of delay's (#) in verilog, like the following snippet : always @(posedge clk) load_r

Hi, I'm a bit confused by the do's and dont's of delay's (#) in verilog, like the following snippet : always @(posedge clk) load_r


How to convert Verilog in to VHDL code

Started by solomon Alemu in comp.arch.fpga11 years ago 2 replies

I have tried to convert the following verilog code manually in to VHDL in order to use it in my project which is written in vhdl. But I am...

I have tried to convert the following verilog code manually in to VHDL in order to use it in my project which is written in vhdl. But I am not able to get the same RTL results. Would you help me in converting the next module or tell me how to instantiate vhdl into verilog please? thanks in advance =======Verilog code========= `timescale 1ns / 1ps module ac97 (ready, command_addr...


Good Verilog reference book: Thomas & Moorby

Started by hdl_book_seller in comp.arch.fpga15 years ago

It's the start of a new semester, quarter or school year, so if you're looking for a solid Verilog reference book, let us recommend Thomas...

It's the start of a new semester, quarter or school year, so if you're looking for a solid Verilog reference book, let us recommend Thomas & Moorby's text "The Verilog Hardware Language" at only $32 -- over 73% off the Amazon price of $119. We are clearing our overstock of the classic Verilog reference text. They are brand new and in the original wrapper, WITH CDROM, and we ship internatio...


Matlab: What do I need for modeling?

Started by Kevin Neilson in comp.arch.fpga18 years ago

I'm not intimately familiar with Matlab, and I'd like to know which pieces I need for a project. Normally I get filter coefficients from...

I'm not intimately familiar with Matlab, and I'd like to know which pieces I need for a project. Normally I get filter coefficients from ScopeFIR, and then go straight to Verilog. Sometimes I model FIR filters, mixers, etc., using behavioral Verilog, but more often than not I just go straight to the synthesizable Verilog. I can simulate this in Modelsim and do a DFT on the results using Sc...


XST vs. Verilog Libraries

Started by Stephen Williams in comp.arch.fpga16 years ago 1 reply

I'm working with ISE 6.2i on a project, and I'm trying to organize the source into libraries. In fact, I'm using a couple Opencores cores for...

I'm working with ISE 6.2i on a project, and I'm trying to organize the source into libraries. In fact, I'm using a couple Opencores cores for this task as well. The libraries are in the format that Icarus Verilog handles just fine. That is, the library is a directory of verilog files, with each file named after the module it contains. I cannot for the life of me figure out how to get XST ...


Modelsim problem - mixed VHDL,Verilog & VHO

Started by Mark McDougall in comp.arch.fpga14 years ago 6 replies

I'm having problems getting a simulation running. Here's the recipe... Quartus output VHO file - contains VHDL & Verilog components. Testbench...

I'm having problems getting a simulation running. Here's the recipe... Quartus output VHO file - contains VHDL & Verilog components. Testbench components - VHDL & Verilog components. Note (and I *think* this is part of the problem) the VHO file contains a certain verilog modle, whilst the testbench also contains an instance of the same module, albeit with *different* parameter values. ...


ModelSim Xilinx edition new bug?

Started by Dan K in comp.arch.fpga14 years ago 2 replies

Xilinx ISE 8.2i service pack 3 ModelSim XE III 6.1e VHDL system When I build a block ram using CoreGen in Xilinx ISE it produces the VHDL...

Xilinx ISE 8.2i service pack 3 ModelSim XE III 6.1e VHDL system When I build a block ram using CoreGen in Xilinx ISE it produces the VHDL file and the Verilog file. When ModelSim sees the verilog file it grabs it and trys to use it but then errors out saying this version of ModelSim does not support a mixed design of both VHDL and Verilog. If I go in and delete the Verilog files eve...


systemc to verilog translator v0.5

Started by Javier Castillo in comp.arch.fpga16 years ago

Hello, We have released the version 0.5 of the SystemC to Verilog Synthesizable Subset Translator, wich includes support for...

Hello, We have released the version 0.5 of the SystemC to Verilog Synthesizable Subset Translator, wich includes support for structures translation from SystemC to Verilog. You can download it from http://www.opencores.org/projects.cgi/web/sc2v/overview Javier Castillo


Verilog inout, I2C

Started by ASIC in comp.arch.fpga10 years ago 9 replies

Hello, I'm trying to create an I2C master module in Verilog. I've never been able to successfully use inout's in Verilog and I'm still unsure...

Hello, I'm trying to create an I2C master module in Verilog. I've never been able to successfully use inout's in Verilog and I'm still unsure why. I compiled my code and ran a test bench and I noticed the signals were at least changing; that is, the inout's seemed to be toggling. After this (although I still don't know if the module is conforming to the I2C bus protocol: baby steps) I decided t...


Verilog examples???

Started by Amir Intisar in comp.arch.fpga16 years ago 3 replies

Hello, does anyone know a good website that has examples of verilog programs you can implement on FPGA's. I have implemented basic programs that...

Hello, does anyone know a good website that has examples of verilog programs you can implement on FPGA's. I have implemented basic programs that use the LED's, switches and push buttons. However, I am looking for verilog programs that can show me how to utilise the I/O expansion sockets, VGA connector and the 7 segment digital display.........Cheers !!!!!!!!!


Very Stupid XST verilog synthesis question...

Started by Nicholas Weaver in comp.arch.fpga16 years ago 4 replies

OK. I'm just braindead, my verilog is horribly rusty, insert tons o excuses here, but... I'm struggling with how the initial condition...

OK. I'm just braindead, my verilog is horribly rusty, insert tons o excuses here, but... I'm struggling with how the initial condition semantics are working in XST's (6.1) verilog synthesizer for inferred registers (target V2pro): All this is being tested by compiling and viewing with a logic analyzer. live_pulse is an input which goes high for a single clock cycle. This is a gross...


Instantiating an lpm dcfifo in Verilog

Started by jjli...@hotmail.com in comp.arch.fpga13 years ago 1 reply

Hello, I know many will say this is not an appropriate group to post such a question, but I wasn't getting any response on the Verilog group, so...

Hello, I know many will say this is not an appropriate group to post such a question, but I wasn't getting any response on the Verilog group, so please let me apologize. I am new to Verilog and need some help instantiating a lpm dcfifo in my code. Here is what I have so far: FIFIN : lpm_fifo_dc WITH (LPM_WIDTH = 64, LPM_NUMWORDS = 64, LPM_WIDTHU = 9, RDSYNC_DELAYPIPE = 3, WRSYNC_D...


Verilog in Quartus and assignments in blocks

Started by Giorgos Tzampanakis in comp.arch.fpga11 years ago 4 replies

I was under the impression that in Verilog nonblocking assignments are evaluated in an arbitrary order. However, in Quartus, I have noticed...

I was under the impression that in Verilog nonblocking assignments are evaluated in an arbitrary order. However, in Quartus, I have noticed that if you use something like this: always @(posedge clock) begin a


Using bidirectional pins in Verilog

Started by Giorgos Tzampanakis in comp.arch.fpga11 years ago 1 reply

I'm trying to use bidirectional pins in Quartus with Verilog. What's the correct way to do it? Altera has some example...

I'm trying to use bidirectional pins in Quartus with Verilog. What's the correct way to do it? Altera has some example code: http://www.altera.com/support/examples/verilog/ver_bidirec.html But I don't really understand it. For example, it says it can drive the value b out but I can't see bidir being assigned to at all, rather just being connected to a when oe is asserted.


Question in verilog testbench

Started by Frank in comp.arch.fpga11 years ago 3 replies

Hi, all I have a question in the testbench written by verilog. Why we always define the inputs of MUT as reg and outputs of MUT as wire, just...

Hi, all I have a question in the testbench written by verilog. Why we always define the inputs of MUT as reg and outputs of MUT as wire, just the opposite with the in/output definition in verilog modules. So more clearly, what are the basic issues that I should know when I have to decide the type of a variable(reg or wire)? Thanks Frank


verilog parser question about `defines

Started by raphfrk in comp.arch.fpga14 years ago 3 replies

I have a set of verilog files that uses `defines. The same `define is applied to each file to select which code to use. Is there a way to...

I have a set of verilog files that uses `defines. The same `define is applied to each file to select which code to use. Is there a way to setup Xilinx ISE so that when processing all verilog files it assumes that a certain `define has been defined ?


Xilinx Johnson counter Verilog example bug?

Started by Chris Carlen in comp.arch.fpga17 years ago 3 replies

Greetings: I have set out to learn Verilog, and thus to learn to use the ModelSim XE II v5.7c Starter simulation program that comes with...

Greetings: I have set out to learn Verilog, and thus to learn to use the ModelSim XE II v5.7c Starter simulation program that comes with Xilink WebPack 5.2i. Yesterday I got the software all installed and ready for today's first venture into my shiny new textbook "A Verilog HDL Primer" by J Bhasker. I began by making sure I knew how to use the software by compiling and simulating ...