Verilog, PSL or SystemVerilog of OVL?

Started by Davy in comp.arch.fpga15 years ago 2 replies

Hi all, I am a Verilog user. I want to use assertion based verification in my project. And I found OVL(Open Verification library). Do you...

Hi all, I am a Verilog user. I want to use assertion based verification in my project. And I found OVL(Open Verification library). Do you think which one of the OVL is better? Verilog, PSL or SystemVerilog? And I heard SystemVerilog have the ABV feature? Why OVL supply ABV in SystemVerilog again? Best regards, Davy


Verilog vs VHDL

Started by Kishore in comp.arch.fpga15 years ago 28 replies

Hi, I know this has been brought up many times in various groups but here is my view on them and I would really appreciate...

Hi, I know this has been brought up many times in various groups but here is my view on them and I would really appreciate some clarification. I started working on FPGA design and stuff some 3 months back or so. All the time I was switching back and forth between verilog and VHDL for various projects. I personally feel that one can be very productive as in time with Verilog? I only us...


How can I see the waveform of my verilog codes?

Started by mikelinyoho in comp.arch.fpga16 years ago 1 reply

Regards: I use "Icarus Verilog" as a synthesis and simulation tool.But How can I see the waveform of my verilog codes? thank you may...

Regards: I use "Icarus Verilog" as a synthesis and simulation tool.But How can I see the waveform of my verilog codes? thank you may goodness be with you all


XST Tool - Want a verilog simulation netlist

Started by Varun Jindal in comp.arch.fpga17 years ago 2 replies

Hello, I want to compare two designs, one of which is written in verilog while the other one is in vhdl. the testcases are also written...

Hello, I want to compare two designs, one of which is written in verilog while the other one is in vhdl. the testcases are also written in verilog. while running the vhdl design, (using XST VHDL) .. the design compiles without error, but i couldnt figure out a way to generate the simulation netlist in verilog for the design. does there exist any such switch using which i can generate a ver...


Initializing inferred components with Xilinx ISE Foundation 6

Started by Matt Hardy in comp.arch.fpga18 years ago 1 reply

Hello, I have a large design implemented in Verilog. In the design there are several thousand SRL16 type shift registers that are inferred...

Hello, I have a large design implemented in Verilog. In the design there are several thousand SRL16 type shift registers that are inferred from the Verilog by XST. What is the best way to initialize each shift register with different a unique value? Preferably this initialization could be specified outside of the verilog so that thousands or different module definitions are not needed. ...


Help with good verilog practices

Started by Sink0 in comp.arch.fpga10 years ago

Hi, i have written the following verilog code. Its basically a WB master to read and write from OC PCI bridge core. Can you guys point me what...

Hi, i have written the following verilog code. Its basically a WB master to read and write from OC PCI bridge core. Can you guys point me what is "ugly" on my code, or what is a bad practice? I just want to learn what is a good practice programming with verilog, and why. `include "network_controller_constants.v" module NETWORK_CONTROLLER_WB_MASTER ( CLK_I, RST_I, MINT_O, M...


VHDL to Verilog Converter

Started by Ambreen Ashfaq Afridi in comp.arch.fpga13 years ago 3 replies

Hi im looking for a vhdl to verilog converter. Im working with Trimode Ethernet MAC core which is written in VHDL. I have to modify this...

Hi im looking for a vhdl to verilog converter. Im working with Trimode Ethernet MAC core which is written in VHDL. I have to modify this code but the problem is that I dont have any knowledge of VHDL. I do programming in Verilog.Plz send me any link for the converter. Thank you Regards, Ambreen Ashfaq


Using both Verilog and VHDL for Xilinx simulation

Started by Michael in comp.arch.fpga9 years ago 1 reply

Hi, How do I setup synopsys_sim.setup for simulating both Verilog and VHDL using VCS for a Xilinx FPGA? I need for instance have SIMPRIM...

Hi, How do I setup synopsys_sim.setup for simulating both Verilog and VHDL using VCS for a Xilinx FPGA? I need for instance have SIMPRIM point to both the VHDL and the Verilog compiled library path, I did try using a : and simply append them but it failed. /michael


dct verilog

Started by Shakes in comp.arch.fpga11 years ago 3 replies

hi, I downloaded the DCT verilog module from the altera website. http://www.altera.com/support/examples/verilog/ver_dct.html I ran a...

hi, I downloaded the DCT verilog module from the altera website. http://www.altera.com/support/examples/verilog/ver_dct.html I ran a simulation using simple testbench that sends 0,1,2,...63 as the input parameters. The dct_out(output signal) never sends out any result and it always xxxxxx. From the initial basic understanding of the code, the reading the writing of local memory seems don...


question about verilog ?, :

Started by fl in comp.arch.fpga8 years ago 6 replies

Hi, I know some VHDL, but totally new to verilog. Now I am reading a verilog template. I do not know the meaning of the following code: ...

Hi, I know some VHDL, but totally new to verilog. Now I am reading a verilog template. I do not know the meaning of the following code: assign ce_hciccomp_decode = (cur_count == 0 && clk_enable == 1'b1)? 1 : (cur_count == 2 && clk_enable == 1'b1)? 1 : (cur_count == 4 && clk_enable == 1'b1)? 1 : ...


Question about filters and verilog etc..

Started by Jan Panteltje in comp.arch.fpga17 years ago 3 replies

I need to make some filters now for some project in FPGA. I was wondering if some free (open source?) software exists that outputs verilog (or a...

I need to make some filters now for some project in FPGA. I was wondering if some free (open source?) software exists that outputs verilog (or a xilinx module for example) with as input say -3dB point, slope, poles, low / high pass etc.? These programs do exist for analog filters, some from IC manufacturers. Is such a thing feasable (to do in verilog) does it exist? Jan


Adding Desing to an Xilins Platform Studio project

Started by Timo Gerber in comp.arch.fpga13 years ago

Hi, I'm trying to add an existing project which successfully synthesized and simulated with ISE 8.2 and Modelsim to an XPS-project. It's...

Hi, I'm trying to add an existing project which successfully synthesized and simulated with ISE 8.2 and Modelsim to an XPS-project. It's verilog / VHDL Mixed, with the top-module being verilog with vhdl and verilog submodules. so I started using the import peripheral wizard, and it is recognizing my .prj file correctly. However I get an error in the HDL Analyzing Step: HDLCompilers:87...


Verilog simple dual port memory with different input and output widths?

Started by davew in comp.arch.fpga14 years ago 2 replies

Has anyone got any example Verilog code for this? I'm currently using Quartus wizard generated code and wrapping it up in a Verilog module so I...

Has anyone got any example Verilog code for this? I'm currently using Quartus wizard generated code and wrapping it up in a Verilog module so I can use my own parameters instead of running the wizard each time I need a new variation (which is a complete pain). I thought that perhaps inferring the memory might yield better and more efficient results. Ta.


Online C-to-FPGA tool

Started by Nadav Rotem in comp.arch.fpga12 years ago 3 replies

Hello, My name is Nadav and I am the author of http://www.C-to-Verilog.com ; This website allows FPGA developers to take regular C code...

Hello, My name is Nadav and I am the author of http://www.C-to-Verilog.com ; This website allows FPGA developers to take regular C code and "compile" it into Verilog. The Verilog code can be verified with the auto generated test-bench and then synthesized to an FPGA. The compiler tries to "pipeline" as much code as possible to get a design which is fast, operates at high frequencies and ta...


Verilog Binary Division

Started by Kristo Godari in comp.arch.fpga8 years ago 15 replies

I need a Verilog behavioral model (verilog behavioral code) for: - unsigned 8-bit division The module I have to use is this one: module...

I need a Verilog behavioral model (verilog behavioral code) for: - unsigned 8-bit division The module I have to use is this one: module divider( output reg[7:0] q, output reg[7:0] r, input [7:0] a,b); endmodule where a=b*q+r Is preferable to use SRT, Newton-Raphson or Goldschmidt algorithms to solve it. Can someone help me?


I2C bus controller Implementation

Started by Julien Lochen in comp.arch.fpga15 years ago 1 reply

Hello, My name is Julien, I work as Design engineer in France. I am currently implementing in Verilog an I2C controller on a...

Hello, My name is Julien, I work as Design engineer in France. I am currently implementing in Verilog an I2C controller on a Xilinx Spartan3, and I need to test it. With the application note XAPP333, Xilinx provides testbenches in VHDL but not in Verilog. Where can I get the testbenches in Verilog ? regards, Julien


Verilog DSP Examples (FFT With 32K-Point Transform Length, FIR, IIR, Discrete Cosine Transform (DCT), Convolution 2D)

Started by Jhoberg in comp.arch.fpga14 years ago

Hi, Here there are some examples in Verilog of functions DSP for FPGAs, some of these...

Hi, Here there are some examples in Verilog of functions DSP for FPGAs, some of these are: http://www.altera.com/support/examples/verilog/verilog.html * Achieving Unity Gain in IFFT+FFT Pair Using Block Floating Point Arithmetic * Fast Fourier Transform (FFT) With 32K-Point Transform Length * Coefficient Reload Finite Impulse Response (FIR) Filter * Discrete Cosine Transform (DCT...


OPB in Verilog

Started by Andres Calderon in comp.arch.fpga17 years ago 1 reply

Somebody can send an example, document or advice to help me in the verilog implementation of a OPB module (EDK 6.2) thanks, -- Andres

Somebody can send an example, document or advice to help me in the verilog implementation of a OPB module (EDK 6.2) thanks, -- Andres


Using Verilog to embed the synthesis date and time

Started by John Providenza in comp.arch.fpga17 years ago 6 replies

Does anyone have a simple way to embed the date and time that a module is compiled into a wire or register in Verilog? I could use a Perl...

Does anyone have a simple way to embed the date and time that a module is compiled into a wire or register in Verilog? I could use a Perl script to create an `include file with the proper `define statements, but I'm wondering if anyone has a cute way to do this purely in Verilog. FYI - I'm using Xilinx XST for synthesis. Thanks! John P


Is there a verilog version of PicoBlaze?

Started by Anonymous in comp.arch.fpga17 years ago 14 replies

Hi all, I have downloaded a VHDL version of PicoBlaze. I can synthesize it with other VHDL modules, my I prefer the use of Verilog, so the...

Hi all, I have downloaded a VHDL version of PicoBlaze. I can synthesize it with other VHDL modules, my I prefer the use of Verilog, so the only way I can use it with them is through EDIF black-box. Anyway, life could be better if I can use a verilog version of PicoBlaze directly. Does anyone know if it exists? Thanks in advance, Santiago.