Re: Trivia: Where are you on the HDL Map?

Started by Chris Maryan in comp.arch.fpga10 years ago

This has been discussed before, though I can't find the thread. The general= pattern is that VHDL/Verilog is about 50/50 in the FPGA world, with...

This has been discussed before, though I can't find the thread. The general= pattern is that VHDL/Verilog is about 50/50 in the FPGA world, with a bias= towards VHDL on the east side of N. America and Europe. The exception is C= alifornia where Verilog dominates FPGA work. ASIC work is largely dominated= by Verilog. I'm not sure what the historical reasons for this pattern are. Generally...


Number of Modules in a Verilog File

Started by Jiten in comp.arch.fpga15 years ago

Hi, Is there any method to increase number of verilog modules/instances in a single verilog file, While sythesizing with Xilinx Project...

Hi, Is there any method to increase number of verilog modules/instances in a single verilog file, While sythesizing with Xilinx Project navigator? If there are more than about 50 modules in a single verilog file it is not taken by project navigator, and it shows a '?' ahead of these modules. Like the modules are missing but actually they are not. If any one have some solution, please put...


problems with verilog SDRAM models

Started by wallge in comp.arch.fpga14 years ago 9 replies

I am trying to write an SDRAM controller in VHDL for a mobile SDR SDRAM that I want to be able to control via an FPGA on the same PCB. I am...

I am trying to write an SDRAM controller in VHDL for a mobile SDR SDRAM that I want to be able to control via an FPGA on the same PCB. I am having trouble with the verilog model. I have used both a samsung and a micron model for the part (two compatible parts). Unfortunately these models are not available in VHDL, and my verilog is pretty weak. I wondered if any one had some experience with...


Verilog-2001 and Xilinx ISE 7.1?

Started by nonoe in comp.arch.fpga16 years ago

When I tried Xilinx Webpack 6.3, I noticed that the XST (Xilinx Synthesis Technology) was missing some Verilog-2001 features. For me, the...

When I tried Xilinx Webpack 6.3, I noticed that the XST (Xilinx Synthesis Technology) was missing some Verilog-2001 features. For me, the showstoppers were no $signed and $unsigned system- tasks. (I know they don't do anything when moving between signed unsigned vectors of identical bit-width, but our RTL uses them to clearly denote the designer's intent.) And lack of Verilog macro-ar


Adding Verilog processing core to Viretx2Pro at ML310

Started by sps in comp.arch.fpga16 years ago 3 replies

Hi, I have a Verilog processing core. I want to implement it on Vertex2Pro device as a separate core , adding it to current bus architecture....

Hi, I have a Verilog processing core. I want to implement it on Vertex2Pro device as a separate core , adding it to current bus architecture. I know that VHDL cores can be added. Is it possible to add Verilog cores? Thanks for the reply. Regards SPS


Task in verilog

Started by FPGA in comp.arch.fpga13 years ago 2 replies

Is task in verilog equivalent to procedure in VHDL? I am trying to convert a verilog file to vhdl. Verilog => // string data type reg...

Is task in verilog equivalent to procedure in VHDL? I am trying to convert a verilog file to vhdl. Verilog => // string data type reg [8*4:1]a; reg [8*255:0]b; VHDL => Is the above equivalent to variable a : string(1 to 8*4) variable b : string(1 to 8*255)


Missing module : XFFT_V3_1 Verilog (not VHDL) module

Started by Vitaliy in comp.arch.fpga14 years ago

Hello, Does anyone know if XFFT_V3_1 Verilog (not VHDL) module (normally found in C:\Modeltech_xe_starter\xilinx\verilog\XilinxCoreLib_ver)...

Hello, Does anyone know if XFFT_V3_1 Verilog (not VHDL) module (normally found in C:\Modeltech_xe_starter\xilinx\verilog\XilinxCoreLib_ver) exists? It was not shipped with ISE7.1i (I have noticed a few people in newsgroups asking similar question), I got the update from Xilinx site but still no luck. If you know, can you please point me to where to -download it -or compress and email it t...


Open source Verilog BCH encoder/decoder

Started by Russell Dill in comp.arch.fpga10 months ago 10 replies

As part of my research, I needed a BCH encoder/decoder engine. Sadly, such = a thing has no existed under a permissive license. Even more...

As part of my research, I needed a BCH encoder/decoder engine. Sadly, such = a thing has no existed under a permissive license. Even more depressing is = that many students seem to submit Verilog or VHDL engines as a project (or = even research), but never release anything that is usable. Anyway, I'm releasing a BSD licensed Verilog BCH encoder/decoder. It offers= : * Parallel input/outp...


.xco file and vcs verilog compiler

Started by Anonymous in comp.arch.fpga14 years ago 2 replies

I have a Xilinx design that uses mainly verilog RTL and some .xco file for coregen FIFOs and such. I am using vcs compiler from synopsys. This...

I have a Xilinx design that uses mainly verilog RTL and some .xco file for coregen FIFOs and such. I am using vcs compiler from synopsys. This compiler does not recgonize the xco files. Is there any way I can convert .xco file into verilog file using Xilinx coregen? I do not know why this shareware design does not provide the verilog file for coregen fifo and instead it has the .xco file. Is th...


Re: Project Navigator / Verilog / +define

Started by Newman in comp.arch.fpga14 years ago

On May 23, 2:48 pm, johnp wrote: > I'm having a problem with Xilinx Navigator "discovering" a Verilog > design hierarchy. > > I've...

On May 23, 2:48 pm, johnp wrote: > I'm having a problem with Xilinx Navigator "discovering" a Verilog > design hierarchy. > > I've inherited some IP that requires that a Verilog `define be set to > specify > the modules to include into the design. However, when Navigator starts > up > and builds the design hierarchy, I see no way to tell it about global > macros


Can't get my Verilog Peripheral to import into XPS! Any tricks?

Started by Anonymous in comp.arch.fpga15 years ago 7 replies

Hello - I am trying to write a custom peripheral using Verilog and version 8.1 of the Xilinx tool kits (ISE and XPS). It is my understanding...

Hello - I am trying to write a custom peripheral using Verilog and version 8.1 of the Xilinx tool kits (ISE and XPS). It is my understanding that only the user_logic component of the peripheral can be developed in Verilog, not sure if that is correct or not. Anyway, I used the XPS create custom peripheral tool to create the skeleton of the peripheral. I was careful to select the option...


How to do one hot state machine in verilog for Xilinx V5 using XST

Started by Anonymous in comp.arch.fpga14 years ago 5 replies

I would like to use one hot state machine in verilog. I am using Xilinx V5 FPGA and XST synthesis tool. May i know the verilog syntex to do...

I would like to use one hot state machine in verilog. I am using Xilinx V5 FPGA and XST synthesis tool. May i know the verilog syntex to do one hot? Thanks. CP


Re: Convert Schematic Files (.sch) to Verilog Files (.v) for simulation in ModelSim

Started by Matthew Hicks in comp.arch.fpga14 years ago 3 replies

Austin, How accurate is the timing for post place and route simulations using the Xilinx libraries? ---Matthew Hicks > Craig, > ...

Austin, How accurate is the timing for post place and route simulations using the Xilinx libraries? ---Matthew Hicks > Craig, > > Depending on what tools you used to capture the schematic, and what > models your flow supports, asking for a "verilog netlist" is a feature > of some tools. > > The resulting verilog netlist will be at the transistor and wire > level, or gate le


mixed Verilog/VHDL in ispLever 7.0 broken

Started by Richard Klingler in comp.arch.fpga14 years ago 2 replies

G'day (o; Just got the confirmation that ispLever 7.0 is broken for mixed Verilog/VHDL designs...my case was that a VHDL T80 Z80 CPU core...

G'day (o; Just got the confirmation that ispLever 7.0 is broken for mixed Verilog/VHDL designs...my case was that a VHDL T80 Z80 CPU core module wrapped in a Verilog top file would fail with Precision unable to find work library... Now with the patch it's running through (o; Either contact Lattice for a fix if you have this issue or wait until end of year for ispLever 7.1 (o; che...


Xilinx PCIe core vs. Icarus Verilog

Started by Stephen Williams in comp.arch.fpga15 years ago 2 replies

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Does anybody know if the Xilinx PCI Express cores from Xilinx can run w/ Icarus Verilog? I...

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Does anybody know if the Xilinx PCI Express cores from Xilinx can run w/ Icarus Verilog? I can't seem to get access to an eval copy to find out for myself. The link to the .tar.gz (and the .zip) seem dead for me. Nor can I find out if I can use it with WebPACK or I need the full ISE to access the actual Verilog. The last full ISE I have is...


Port mapping a Verilog component in a VHDL design

Started by ALuPin in comp.arch.fpga17 years ago 2 replies

Dear Sir or Madam, I have the following problem: I have a simulation component which is written in Verilog (not a trivial one which could...

Dear Sir or Madam, I have the following problem: I have a simulation component which is written in Verilog (not a trivial one which could be translated to VHDL). My toplevel design and all other components are written in VHDL. My question: Is it possible to include this Verilog component in my VHDL top level ? What about the types std_logic / std_logic_vector ? Can I connect the...


CPU Model for Co-simulation

Started by akineko in comp.arch.fpga13 years ago 2 replies

Hello everyone, I would like to create a scheme to hook up an external CPU model to a Verilog design. I have already established a basic...

Hello everyone, I would like to create a scheme to hook up an external CPU model to a Verilog design. I have already established a basic communication protocol to link Verilog design to an external device. So, it should be easy to link a CPU model to a Verilog design. I'm looking for a 32-bit CPU model written in C or Java or Python or any high-level language that can be supported by gc...


Project Navigator / Verilog / +define

Started by johnp in comp.arch.fpga14 years ago

I'm having a problem with Xilinx Navigator "discovering" a Verilog design hierarchy. I've inherited some IP that requires that a Verilog...

I'm having a problem with Xilinx Navigator "discovering" a Verilog design hierarchy. I've inherited some IP that requires that a Verilog `define be set to specify the modules to include into the design. However, when Navigator starts up and builds the design hierarchy, I see no way to tell it about global macros definitions. I can manually go in and add `define values in the files (yu...


Project Navigator / Verilog / +define

Started by johnp in comp.arch.fpga14 years ago

I'm having a problem with Xilinx Navigator "discovering" a Verilog design hierarchy. I've inherited some IP that requires that a Verilog...

I'm having a problem with Xilinx Navigator "discovering" a Verilog design hierarchy. I've inherited some IP that requires that a Verilog `define be set to specify the modules to include into the design. However, when Navigator starts up and builds the design hierarchy, I see no way to tell it about global macros definitions. I can manually go in and add `define values in the files (yu...


Xilinx XST 6.x and Verilog-2001?

Started by Allan Herriman in comp.arch.fpga18 years ago 1 reply

Hi, Does Xilinx XST 6.x support RTL-synthesis of Verilog-2001? This...

Hi, Does Xilinx XST 6.x support RTL-synthesis of Verilog-2001? This document http://toolbox.xilinx.com/docsan/xilinx5/data/docs/xst/xst0083_11.html shows that the older version, XST 5.x, has partial support for Verilog 2001. I was wondering if the support is better in the newer version of ISE. In particular, I'm interested in knowing if 'generate' works, and whether arrays of inst...