Can't get my Verilog Peripheral to import into XPS! Any tricks?

Started by Anonymous in comp.arch.fpga12 years ago 7 replies

Hello - I am trying to write a custom peripheral using Verilog and version 8.1 of the Xilinx tool kits (ISE and XPS). It is my understanding...

Hello - I am trying to write a custom peripheral using Verilog and version 8.1 of the Xilinx tool kits (ISE and XPS). It is my understanding that only the user_logic component of the peripheral can be developed in Verilog, not sure if that is correct or not. Anyway, I used the XPS create custom peripheral tool to create the skeleton of the peripheral. I was careful to select the option...


Quartus II - Generating Verilog from MegaWizard plugins

Started by Giorgos Tzampanakis in comp.arch.fpga9 years ago

I'm using the MegaWizard plugin manager on Quartus II 9.1 on linux and I can't get it to generate any Verilog files for me. It does generate...

I'm using the MegaWizard plugin manager on Quartus II 9.1 on linux and I can't get it to generate any Verilog files for me. It does generate VHDL files. There is an option to generate Verilog but it generates VHDL as far as I can see.


Icarus Verilog opinions

Started by Giorgos Tzampanakis in comp.arch.fpga9 years ago 1 reply

I've been trying out the Icarus Verilog compiler/simulator. It looks nice so far. Any views on it? Also, it claims that it can generate code...

I've been trying out the Icarus Verilog compiler/simulator. It looks nice so far. Any views on it? Also, it claims that it can generate code to load onto real FPGA's. Can it really do that? Has anyone tried it? I'm interested in Altera devices.


New HDLmaker release, Virtex4 support added

Started by B. Joshua Rosen in comp.arch.fpga14 years ago

I've added Virtex4 support to HDLmaker. The new version, 7.2.5, is on the web at http://www.polybus.com/hdlmaker/users_guide/ HDLmaker is a...

I've added Virtex4 support to HDLmaker. The new version, 7.2.5, is on the web at http://www.polybus.com/hdlmaker/users_guide/ HDLmaker is a free hierarchical Verilog generator licensed under a BSD style license. It generates hierarchical Verilog, simulation and synthesis scripts, pad rings, hyperlinked HTML versions of the Verilog code, schematics, and PADS PCB netlists. It also has a C ...


Verilog Coding Guidelines

Started by Pistony2k in comp.arch.fpga13 years ago 1 reply

Hello All, I spent few weeks researching different books and my experience in verilog to write this detailed article. Hopefully, it will be...

Hello All, I spent few weeks researching different books and my experience in verilog to write this detailed article. Hopefully, it will be useful to you. Please check it out and let me know your feedback. http://www.inno-logic.com/tech-forum/viewtopic.php?t=20 Regards, Pistony2k


Verilog Coding Guidelines

Started by Pistony2k in comp.arch.fpga13 years ago

Hello All, I spent few weeks researching different books and my experience in verilog to write this detailed article. Hopefully, it will be...

Hello All, I spent few weeks researching different books and my experience in verilog to write this detailed article. Hopefully, it will be useful to you. Please check it out and let me know your feedback. http://www.inno-logic.com/tech-forum/viewtopic.php?t=20 Regards, Pistony2k


quartus and VHDL/Verilog libraries

Started by Michael Laajanen in comp.arch.fpga13 years ago 1 reply

HI, I am very new to Quartus(5.1 Solaris) and looking for simulation libraries for both Verilog and VHDL, vhdl seams to be found in the...

HI, I am very new to Quartus(5.1 Solaris) and looking for simulation libraries for both Verilog and VHDL, vhdl seams to be found in the install tree but verilog? When I used Xilinx I always started compiling a simulation libraries once for all into the installation tree for each simulator to use, how is this done i Quartus? cheers Michael


Re: Getting started with VHDL and Verilog

Started by Andreas Ehliar in comp.arch.fpga11 years ago 7 replies

On 2008-05-06, jraj.thakkar@gmail.com wrote: > Hi all, > > My background is in Software Engineering C,C++,Java and Unix. I am > getting...

On 2008-05-06, jraj.thakkar@gmail.com wrote: > Hi all, > > My background is in Software Engineering C,C++,Java and Unix. I am > getting started with VHDL and Verilog. What is the good way/books/ > websites/training to get started? I have B.S. and M.S. in Computer > Engineering. Also, what is the learning curve in VHDL and Verilog? Have you ever taken a course in d


Verilog Editor.

Started by Eli Hughes in comp.arch.fpga13 years ago 18 replies

Check out the Zeus Editor. www.zeusedit.com Is is very lost cost and now supports Verilog files with nice code folding! (begin/end ...

Check out the Zeus Editor. www.zeusedit.com Is is very lost cost and now supports Verilog files with nice code folding! (begin/end case/endcase) -Eli


.xco file and vcs verilog compiler

Started by Anonymous in comp.arch.fpga11 years ago 2 replies

I have a Xilinx design that uses mainly verilog RTL and some .xco file for coregen FIFOs and such. I am using vcs compiler from synopsys. This...

I have a Xilinx design that uses mainly verilog RTL and some .xco file for coregen FIFOs and such. I am using vcs compiler from synopsys. This compiler does not recgonize the xco files. Is there any way I can convert .xco file into verilog file using Xilinx coregen? I do not know why this shareware design does not provide the verilog file for coregen fifo and instead it has the .xco file. Is th...


Xilinx ISE and Verilog $signed/$unsigned tasks?

Started by actela in comp.arch.fpga14 years ago

In ISE Webpack 6.2i, XST (Xilinx Synthesis Technology) supports Verilog-2001 signed operators and datatypes. However, for some reason, it...

In ISE Webpack 6.2i, XST (Xilinx Synthesis Technology) supports Verilog-2001 signed operators and datatypes. However, for some reason, it doesn't support $signed and $unsigned. I mention this, because I frequently use the $signed and $unsigned calls to explicitly force type-conversion. I know the Verilog simulator/compiler doesn't care, but I use $signed/$unsigned for documentation and ...


CPU Model for Co-simulation

Started by akineko in comp.arch.fpga10 years ago 2 replies

Hello everyone, I would like to create a scheme to hook up an external CPU model to a Verilog design. I have already established a basic...

Hello everyone, I would like to create a scheme to hook up an external CPU model to a Verilog design. I have already established a basic communication protocol to link Verilog design to an external device. So, it should be easy to link a CPU model to a Verilog design. I'm looking for a 32-bit CPU model written in C or Java or Python or any high-level language that can be supported by gc...


Verilog, PSL or SystemVerilog of OVL?

Started by Davy in comp.arch.fpga13 years ago 2 replies

Hi all, I am a Verilog user. I want to use assertion based verification in my project. And I found OVL(Open Verification library). Do you...

Hi all, I am a Verilog user. I want to use assertion based verification in my project. And I found OVL(Open Verification library). Do you think which one of the OVL is better? Verilog, PSL or SystemVerilog? And I heard SystemVerilog have the ABV feature? Why OVL supply ABV in SystemVerilog again? Best regards, Davy


Verilog Programmer / FPGA Analyst

Started by Robert in comp.arch.fpga12 years ago

Verilog Programmer / FPGA Analyst Germantown, MD 20874 6 Month Contract With Potential for Extension Summary: We are seeking someone who...

Verilog Programmer / FPGA Analyst Germantown, MD 20874 6 Month Contract With Potential for Extension Summary: We are seeking someone who knows the C programming language and has experience with Xilinx FPGA development and the Verilog programming language. If you have questions feel free to email or IM me before submitting your resume. Location: Germantown, MD - This location is 30 min...


(Improve Verilog skill) Recommend CPU core with good document and coding?

Started by Shenli in comp.arch.fpga12 years ago 3 replies

Hi all, These days, I found my Verilog code reading speed is not fast like my C/C++ reading speed. It take me a lot of time to understand...

Hi all, These days, I found my Verilog code reading speed is not fast like my C/C++ reading speed. It take me a lot of time to understand Verilog code than C/C++ code. So, I want to read through a small CPU core (I prefer line


Xilinx ISE 6.3 verilog simulation problem

Started by Big Boy in comp.arch.fpga14 years ago 4 replies

I'm still new in FPGA design, and learning Verilog, and the EDA tool (Xilinx ISE, ModelSim, ...) I have a problem simulating Post-Map...

I'm still new in FPGA design, and learning Verilog, and the EDA tool (Xilinx ISE, ModelSim, ...) I have a problem simulating Post-Map Simulation Model with ISE 6.3. I have a verilog project which consist of 2 files (a simple module an a test bench). My module file contain a module with ports defined as module mux4_to_1(out, i0, i1, i2, i3, s1, s0); And, from the testbench file, I inst...


how can I simulate the vhdl and verilog mixed design in modelsim?

Started by Jimmy in comp.arch.fpga14 years ago 2 replies

Hi, all , I am using ISE6.2 and modelsim5.8b. My design is composed of two modules, one is VDHL design ,and the other is verilog design....

Hi, all , I am using ISE6.2 and modelsim5.8b. My design is composed of two modules, one is VDHL design ,and the other is verilog design. Now I want to combine them together in a top level file (in vhdl) and simulate the whole design. Can I just instantiate the verilog design module with a compoenent in the top file and write a testbench for the top file. I have done this , but it f...


Xilinx XST 6.x and Verilog-2001?

Started by Allan Herriman in comp.arch.fpga15 years ago 1 reply

Hi, Does Xilinx XST 6.x support RTL-synthesis of Verilog-2001? This...

Hi, Does Xilinx XST 6.x support RTL-synthesis of Verilog-2001? This document http://toolbox.xilinx.com/docsan/xilinx5/data/docs/xst/xst0083_11.html shows that the older version, XST 5.x, has partial support for Verilog 2001. I was wondering if the support is better in the newer version of ISE. In particular, I'm interested in knowing if 'generate' works, and whether arrays of inst...


Verilog DSP Examples (FFT With 32K-Point Transform Length, FIR, IIR, Discrete Cosine Transform (DCT), Convolution 2D)

Started by Jhoberg in comp.arch.fpga12 years ago

Hi, Here there are some examples in Verilog of functions DSP for FPGAs, some of these...

Hi, Here there are some examples in Verilog of functions DSP for FPGAs, some of these are: http://www.altera.com/support/examples/verilog/verilog.html * Achieving Unity Gain in IFFT+FFT Pair Using Block Floating Point Arithmetic * Fast Fourier Transform (FFT) With 32K-Point Transform Length * Coefficient Reload Finite Impulse Response (FIR) Filter * Discrete Cosine Transform (DCT...


VHDL or Verilog?

Started by Rick C. Hodgin in comp.arch.fpga1 year ago 20 replies

I've been given conflicting device on which language to use. There are people I would consider to be expert professionals who tell me to use...

I've been given conflicting device on which language to use. There are people I would consider to be expert professionals who tell me to use VHDL, and others who tell me Verilog. Most everybody tells me that if I use VHDL there's less chance for error, but that it does take more effort to learn. Any thoughts? Thank you, Rick C. Hodgin