Xilinx ISE 6.3 verilog simulation problem

Started by Big Boy in comp.arch.fpga16 years ago 4 replies

I'm still new in FPGA design, and learning Verilog, and the EDA tool (Xilinx ISE, ModelSim, ...) I have a problem simulating Post-Map...

I'm still new in FPGA design, and learning Verilog, and the EDA tool (Xilinx ISE, ModelSim, ...) I have a problem simulating Post-Map Simulation Model with ISE 6.3. I have a verilog project which consist of 2 files (a simple module an a test bench). My module file contain a module with ports defined as module mux4_to_1(out, i0, i1, i2, i3, s1, s0); And, from the testbench file, I inst...


configuration for a mixed mode VHDL-verilog lang

Started by Rakesh YC in comp.arch.fpga17 years ago 1 reply

Hi all My problem is I'd like to choose a VHDL file instantiated inside verilog via VHDL configuration To summerize: I have a hierarcy:...

Hi all My problem is I'd like to choose a VHDL file instantiated inside verilog via VHDL configuration To summerize: I have a hierarcy: "top:vhdl - verilog - Verlog -vhdl: bottom" How to write a vhdl configuration to select the file for the bottom instantiation? Rakesh YC


how can I simulate the vhdl and verilog mixed design in modelsim?

Started by Jimmy in comp.arch.fpga17 years ago 2 replies

Hi, all , I am using ISE6.2 and modelsim5.8b. My design is composed of two modules, one is VDHL design ,and the other is verilog design....

Hi, all , I am using ISE6.2 and modelsim5.8b. My design is composed of two modules, one is VDHL design ,and the other is verilog design. Now I want to combine them together in a top level file (in vhdl) and simulate the whole design. Can I just instantiate the verilog design module with a compoenent in the top file and write a testbench for the top file. I have done this , but it f...


System Verilog 2D input port?

Started by John Smith in comp.arch.fpga10 years ago 1 reply

Is it acceptable to have 2D input ports using System Verilog? I know it's not possible in Verilog. The only workaround I could think of is to...

Is it acceptable to have 2D input ports using System Verilog? I know it's not possible in Verilog. The only workaround I could think of is to 'flatten' out the input port and use it; but that seems to be messy inside loops. Is there any other workaround?


why systemc?

Started by Anonymous in comp.arch.fpga17 years ago 15 replies

Hi, Can anybody elaborate on the speed of the simulation in systemC in comparision with Verilog. In our case we have used the systemC for the...

Hi, Can anybody elaborate on the speed of the simulation in systemC in comparision with Verilog. In our case we have used the systemC for the modeling of RTL design, then verified the systemC RTL models. As a final step systemC RTL is converted into verilog RTL(line by line translation). we are surprised to see the both systemC models and Verilog models are running at almost same speed. C...


New HDLmaker release, Virtex4 support added

Started by B. Joshua Rosen in comp.arch.fpga17 years ago

I've added Virtex4 support to HDLmaker. The new version, 7.2.5, is on the web at http://www.polybus.com/hdlmaker/users_guide/ HDLmaker is a...

I've added Virtex4 support to HDLmaker. The new version, 7.2.5, is on the web at http://www.polybus.com/hdlmaker/users_guide/ HDLmaker is a free hierarchical Verilog generator licensed under a BSD style license. It generates hierarchical Verilog, simulation and synthesis scripts, pad rings, hyperlinked HTML versions of the Verilog code, schematics, and PADS PCB netlists. It also has a C ...


Xilinx ISE and Verilog $signed/$unsigned tasks?

Started by actela in comp.arch.fpga17 years ago

In ISE Webpack 6.2i, XST (Xilinx Synthesis Technology) supports Verilog-2001 signed operators and datatypes. However, for some reason, it...

In ISE Webpack 6.2i, XST (Xilinx Synthesis Technology) supports Verilog-2001 signed operators and datatypes. However, for some reason, it doesn't support $signed and $unsigned. I mention this, because I frequently use the $signed and $unsigned calls to explicitly force type-conversion. I know the Verilog simulator/compiler doesn't care, but I use $signed/$unsigned for documentation and ...


VHDL-Verilog Co-Simulation

Started by raj in comp.arch.fpga17 years ago 1 reply

Hi, I have my design files in Verilog,but want to have my testbenches in VHDL.I think this is possible. Can anybody suggest some pointers to...

Hi, I have my design files in Verilog,but want to have my testbenches in VHDL.I think this is possible. Can anybody suggest some pointers to this. I am using ModelSim 5.7g and Xilinx Project Navigator 6.2. --raj


using (verilog) reg as memory

Started by Anonymous in comp.arch.fpga16 years ago 5 replies

Hi Someone must have ask this question before. Is it a good idea to use verilog's reg to declare a large block of memory and expect it will...

Hi Someone must have ask this question before. Is it a good idea to use verilog's reg to declare a large block of memory and expect it will be synthesizable? Thanks


Differences between Verilog versions

Started by Giorgos Tzampanakis in comp.arch.fpga11 years ago 3 replies

Where can I find a listing of the features that were added to Verilog in the 2001 version, and then of the ones added in SystemVerilog?

Where can I find a listing of the features that were added to Verilog in the 2001 version, and then of the ones added in SystemVerilog?


ports of multidimentional arrays in verilog.

Started by CMOS in comp.arch.fpga15 years ago 2 replies

hi, using verilog how to write a module which has an inpput port for an array of 8 bit signals and how to write a test bench for it. thank...

hi, using verilog how to write a module which has an inpput port for an array of 8 bit signals and how to write a test bench for it. thank you. CMOS


verilog code for read write in Bram block

Started by rajiv in comp.arch.fpga14 years ago 1 reply

Hi all, i am designing a system in which we have a bram block,microblaze processor and other essential component.i have written verilog...

Hi all, i am designing a system in which we have a bram block,microblaze processor and other essential component.i have written verilog code for bram controller .i have to call this verilog code by a c programe. C code is: #include "stdio.h" #include "xparameters.h" #include "xuartlite_l.h" #include "mb_interface.h" int main(void) { int i,j,k; int *mem; int fill_value = 0x...


Verilog Coding Guidelines

Started by Pistony2k in comp.arch.fpga16 years ago 1 reply

Hello All, I spent few weeks researching different books and my experience in verilog to write this detailed article. Hopefully, it will be...

Hello All, I spent few weeks researching different books and my experience in verilog to write this detailed article. Hopefully, it will be useful to you. Please check it out and let me know your feedback. http://www.inno-logic.com/tech-forum/viewtopic.php?t=20 Regards, Pistony2k


Verilog Coding Guidelines

Started by Pistony2k in comp.arch.fpga16 years ago

Hello All, I spent few weeks researching different books and my experience in verilog to write this detailed article. Hopefully, it will be...

Hello All, I spent few weeks researching different books and my experience in verilog to write this detailed article. Hopefully, it will be useful to you. Please check it out and let me know your feedback. http://www.inno-logic.com/tech-forum/viewtopic.php?t=20 Regards, Pistony2k


(Improve Verilog skill) Recommend CPU core with good document and coding?

Started by Shenli in comp.arch.fpga14 years ago 3 replies

Hi all, These days, I found my Verilog code reading speed is not fast like my C/C++ reading speed. It take me a lot of time to understand...

Hi all, These days, I found my Verilog code reading speed is not fast like my C/C++ reading speed. It take me a lot of time to understand Verilog code than C/C++ code. So, I want to read through a small CPU core (I prefer line


New release of SystemC to Verilog translator

Started by Javier Castillo in comp.arch.fpga16 years ago

Hello: OpenSoc Design has released version 0.2 of its SystemC to Verilog Synthesizable subset translator. This release includes: -...

Hello: OpenSoc Design has released version 0.2 of its SystemC to Verilog Synthesizable subset translator. This release includes: - Support for C++ enumerate data types - More SystemC constructions supported - Directives to support custom translation as: -//Translate off, //Translate on: To avoid translate some areas of code -//Verilog, //EndVerilog: To indicate the translator to not...


Verilog Editor.

Started by Eli Hughes in comp.arch.fpga15 years ago 18 replies

Check out the Zeus Editor. www.zeusedit.com Is is very lost cost and now supports Verilog files with nice code folding! (begin/end ...

Check out the Zeus Editor. www.zeusedit.com Is is very lost cost and now supports Verilog files with nice code folding! (begin/end case/endcase) -Eli


Quartus II - Generating Verilog from MegaWizard plugins

Started by Giorgos Tzampanakis in comp.arch.fpga11 years ago

I'm using the MegaWizard plugin manager on Quartus II 9.1 on linux and I can't get it to generate any Verilog files for me. It does generate...

I'm using the MegaWizard plugin manager on Quartus II 9.1 on linux and I can't get it to generate any Verilog files for me. It does generate VHDL files. There is an option to generate Verilog but it generates VHDL as far as I can see.


Most popular VHDL/Verilog

Started by Philippe in comp.arch.fpga10 years ago 1 reply

Hi everybody. Could you please help me find out which is the most popular VHDL/ Verilog editor, by filling out this poll:...

Hi everybody. Could you please help me find out which is the most popular VHDL/ Verilog editor, by filling out this poll: http://www.vhdleditor.com/poll I'm not looking for the "best VHDL/Verilog editor" (that would only get a flame war started). I'm just trying to find out which is used more often. So, please go and vote! thanks Philippe


verilog simulation of LogiCORE Complex Multiplier v2.1

Started by Vivek Menon in comp.arch.fpga13 years ago

I instantiated a complex multiplier core using Coregen and I was surprised to see that the module CMPY_V2_1.v called in the coregen verilog file...

I instantiated a complex multiplier core using Coregen and I was surprised to see that the module CMPY_V2_1.v called in the coregen verilog file is not available in the /usr/local/xilinx/ise92i_sp3/ verilog/src/XilinxCoreLib directory. However, the VHDL version of the core is available. (/usr/local/xilinx/ise92i_sp3/vhdl/src/ XilinxCoreLib/cmpy_v2_1.vhd) The Verilog version of the core is ...