microcode in verilog?

Started by Jale...@gmail.com in comp.arch.fpga14 years ago 5 replies

Dear all, I am new to both FPGA and CPU design. I am supposed to implement a CPU on FPGA. The CPU is described in www.homebrewcpu.com. It...

Dear all, I am new to both FPGA and CPU design. I am supposed to implement a CPU on FPGA. The CPU is described in www.homebrewcpu.com. It needs to be exactly the same. Currently I am working on translating the microcodes into verilog. It just seems too complex currently and I do not know where I can seek for more information on how to do this. Any advice or guidance will be much appreciate...


Icarus Verilog opinions

Started by Giorgos Tzampanakis in comp.arch.fpga11 years ago 1 reply

I've been trying out the Icarus Verilog compiler/simulator. It looks nice so far. Any views on it? Also, it claims that it can generate code...

I've been trying out the Icarus Verilog compiler/simulator. It looks nice so far. Any views on it? Also, it claims that it can generate code to load onto real FPGA's. Can it really do that? Has anyone tried it? I'm interested in Altera devices.


quartus and VHDL/Verilog libraries

Started by Michael Laajanen in comp.arch.fpga15 years ago 1 reply

HI, I am very new to Quartus(5.1 Solaris) and looking for simulation libraries for both Verilog and VHDL, vhdl seams to be found in the...

HI, I am very new to Quartus(5.1 Solaris) and looking for simulation libraries for both Verilog and VHDL, vhdl seams to be found in the install tree but verilog? When I used Xilinx I always started compiling a simulation libraries once for all into the installation tree for each simulator to use, how is this done i Quartus? cheers Michael


USB PHY

Started by Anonymous in comp.arch.fpga12 years ago 6 replies

Hi, While searching for USB IP resources on the net I came across USB PHY cores in verilog. 1) Why is it neessary to seperate USB...

Hi, While searching for USB IP resources on the net I came across USB PHY cores in verilog. 1) Why is it neessary to seperate USB controller and PHY in two different cores? It may be necessary for 3.0 due to higher speeds but what is the need for 1.1 and 2.0? 2) If USB PHY is a mixed (Analog & Digital) solution how can it be offered only in verilog as developer claims? How can a mixe...


Re: Getting started with VHDL and Verilog

Started by Andreas Ehliar in comp.arch.fpga13 years ago 7 replies

On 2008-05-06, jraj.thakkar@gmail.com wrote: > Hi all, > > My background is in Software Engineering C,C++,Java and Unix. I am > getting...

On 2008-05-06, jraj.thakkar@gmail.com wrote: > Hi all, > > My background is in Software Engineering C,C++,Java and Unix. I am > getting started with VHDL and Verilog. What is the good way/books/ > websites/training to get started? I have B.S. and M.S. in Computer > Engineering. Also, what is the learning curve in VHDL and Verilog? Have you ever taken a course in d


EDA tool for testing HDL designs (new update) - www.hightech-td.com

Started by vladimir in comp.arch.fpga17 years ago

TBGenerator - program for testing and diagnosting HDL designs (Verilog or VHDL). This program reads source files (VHDL or Verilog) and...

TBGenerator - program for testing and diagnosting HDL designs (Verilog or VHDL). This program reads source files (VHDL or Verilog) and automatically generates test bench file (Verilog or VHDL format) for the selected module and macro file (Tcl/Tk, Sh) for particular simulator (ModelSim, Active-HDL/Riviera, NC-sim, VCSi and others). You don't have to waste your time for writing test benches! ...


I2C Master in Verilog

Started by Chris in comp.arch.fpga14 years ago 2 replies

The opencores.org I2C appears to be only in VHDL. Does anyone know of a free I2C master in Verilog? Thanks, Chris.

The opencores.org I2C appears to be only in VHDL. Does anyone know of a free I2C master in Verilog? Thanks, Chris.


Is it illegal to use an (enum) as a Verilog function input?

Started by Kevin Simonson in comp.arch.fpga8 months ago 1 reply

I'm still very much interested in finding out whether or not it's possible for a Verilog function to have a boolean value as input, but while I...

I'm still very much interested in finding out whether or not it's possible for a Verilog function to have a boolean value as input, but while I was waiting for input on that I decided to rewrite a version of my Verilog code to use an (enum) instead of a (boolean). Much to my amazement, it appears that I can't use an (enum) as an input to a function either! I wrote the following code


Verilog Programmer / FPGA Analyst

Started by Robert in comp.arch.fpga14 years ago

Verilog Programmer / FPGA Analyst Germantown, MD 20874 6 Month Contract With Potential for Extension Summary: We are seeking someone who...

Verilog Programmer / FPGA Analyst Germantown, MD 20874 6 Month Contract With Potential for Extension Summary: We are seeking someone who knows the C programming language and has experience with Xilinx FPGA development and the Verilog programming language. If you have questions feel free to email or IM me before submitting your resume. Location: Germantown, MD - This location is 30 min...


Active-HDL 7.3 web-eval and Xilinx 9.2i.04 Smartmodel simulation?

Started by talkb in comp.arch.fpga13 years ago 2 replies

Has anyone succesfully used Aldec Active HDL 7.3 (web-eval) with a (Verilog) Smartmodel simulation? I'm using Xilinx Webpack 9.2i.04...

Has anyone succesfully used Aldec Active HDL 7.3 (web-eval) with a (Verilog) Smartmodel simulation? I'm using Xilinx Webpack 9.2i.04 (IP-Update#2), and I separately downloaded and installed the Aldec Verilog library-update for 9.2i.04. In Coregen 9.2i.04 (IPUpdate#2), I created a Verilog Virtex5/LXT50 TEMAC. I compiled the core-generated testbench, then added it to my Aldec design-spa...


VHDL or Verilog?

Started by Rick C. Hodgin in comp.arch.fpga4 years ago 20 replies

I've been given conflicting device on which language to use. There are people I would consider to be expert professionals who tell me to use...

I've been given conflicting device on which language to use. There are people I would consider to be expert professionals who tell me to use VHDL, and others who tell me Verilog. Most everybody tells me that if I use VHDL there's less chance for error, but that it does take more effort to learn. Any thoughts? Thank you, Rick C. Hodgin


Xilinx Webpack 6.2 and Verilog `define ?

Started by nospam in comp.arch.fpga17 years ago 1 reply

I've tried to define a macro-expansion in some Verilog-RTL ... `define MAXIMUM2( x, y ) ( ((x)> (y)) ? (x) : (y) ) ... parameter IN_WIDTH...

I've tried to define a macro-expansion in some Verilog-RTL ... `define MAXIMUM2( x, y ) ( ((x)> (y)) ? (x) : (y) ) ... parameter IN_WIDTH = 24; parameter OUT_WIDTH = 32; parameter BUS_WIDTH = `MAXIMUM2( IN_WIDTH, OUT_WIDTH ); This compiles and evalutates correctly under Modelsim 5.6, NC-Verilog 4.0, Design Compiler 2003.06-SP1, etc. But Xilinx Webpack 6.2i spits out an error messa


Mystery CLKDLL, IBUFG, BUFG modules in verilog src (ISE 6.3.03i)

Started by Anonymous in comp.arch.fpga15 years ago 3 replies

Folks, [Beginner] I've been trying to decypher a reference design that contains verilog source and instantiation of modules CLKDLL, IBUFG,...

Folks, [Beginner] I've been trying to decypher a reference design that contains verilog source and instantiation of modules CLKDLL, IBUFG, and BUFG. Reading through the source, seven_seg.v, I find the instantiation of objects CLKDLL, IBUFG, and BUFG, but no source verilog for them. It was provided with development board Xilinx Spartan-3 LC Kit from Avnet*. I am using ISE 6.3.03i from Xilin...


verilog to blif(lut)

Started by junaid in comp.arch.fpga16 years ago 8 replies

Hi All, Can anyone suggest a method to convert verilog file into blif (LUT) format. Does altera or xilinx support this file conversion ?....

Hi All, Can anyone suggest a method to convert verilog file into blif (LUT) format. Does altera or xilinx support this file conversion ?. Kindly help me in this regard Thanking you in advance


VHDL Project Verilog open core compatibility?

Started by Cy Drollinger in comp.arch.fpga17 years ago 1 reply

I am interested in the compatibility of a VHDL project instantiating a verilog open core, floating point arthmetic block. Is this possible and...

I am interested in the compatibility of a VHDL project instantiating a verilog open core, floating point arthmetic block. Is this possible and if it is not is there another way to use a verilog open core inside a VHDL project, a transform of some kind?


VHDL clocking scheme VS Verilog clocking scheme

Started by Anonymous in comp.arch.fpga14 years ago 3 replies

Hi, I am confused about the clocking scheme of the two most popular hdl. The most common usage of clock and reset signal is clk'event clk=3D1...

Hi, I am confused about the clocking scheme of the two most popular hdl. The most common usage of clock and reset signal is clk'event clk=3D1 or reset=3D1. As you see reset signal seem to be a level sensitive as it should be. But in verilog the common structure for clocking is posedge clk or negedge reset. As you see there is an edge constraint for reset signal in verilog. Why this is diff...


Can Verilog codes be synthesized with XIlinx XST?

Started by Kelv...@ SG in comp.arch.fpga17 years ago 1 reply

Hi, there: Can Xilinx XST synthesize encrypted verilog source codes? For example the following style... What is the software to do this...

Hi, there: Can Xilinx XST synthesize encrypted verilog source codes? For example the following style... What is the software to do this encryption? Best Regards, Kelvin


BFM and Verilog custom IP

Started by Anonymous in comp.arch.fpga14 years ago

I'm attempting to use the CoreConnect BFM with a Verilog-based PLB peripheral (for a PowerPC-based design). I used the wizard to generate all of...

I'm attempting to use the CoreConnect BFM with a Verilog-based PLB peripheral (for a PowerPC-based design). I used the wizard to generate all of the VHDL parent and simulation files -- when I try to use the bfm_system project in XPS and run Modelsim, however, I run into a few issues. The first is that the unisims_ver library is not automatically being mapped at some point (even though it's in...


Re: I'd rather switch than fight!

Started by Muzaffer Kal in comp.arch.fpga11 years ago

On Fri, 23 Apr 2010 08:32:48 -0700 (PDT), Jan Decaluwe wrote: > So this is now already the third post that I devote to explaining > to two...

On Fri, 23 Apr 2010 08:32:48 -0700 (PDT), Jan Decaluwe wrote: > So this is now already the third post that I devote to explaining > to two seasoned Verilog designers how a very simple example in > their favourite language with the ultra-short learning curve > actually works. I'm beginning to think that Verilog designers > don't know how to use variables :-) > Actually it


bin hot gray jedi encoding in ISE

Started by Anonymous in comp.arch.fpga17 years ago 1 reply

Hello I have some state machines in kiss which I am converting to the verilog format. I would like to encode this verilog with binary, 1-hot,...

Hello I have some state machines in kiss which I am converting to the verilog format. I would like to encode this verilog with binary, 1-hot, jedi and gray and after that to synthetize them in ISE. I have tried to find out how to do it, but I was unsuccessful Do someone knows the solution thank you in advance regards Dominik