Voila: Nedit macro to produce verilog module instantiations

Started by Timothy Miller in comp.arch.fpga18 years ago 5 replies

I am a user of Nedit (nedit.org) and I do a lot of Verilog coding. When coding verilog modules, you have a module definition which takes one...

I am a user of Nedit (nedit.org) and I do a lot of Verilog coding. When coding verilog modules, you have a module definition which takes one form, and you have a module instantiation which takes another form. Even with columnar copy/paste/search/replace, it can be a tedious process to convert one to the other. Thus, I humbly offer a Nedit macro I wrote that converts a module definition (he...


Simple Counter in Verilog

Started by Anonymous in comp.arch.fpga17 years ago 6 replies

I am moving onto Verilog now from VHDL due to it being too complicated for me to start off with and not having any calsses available to go to in...

I am moving onto Verilog now from VHDL due to it being too complicated for me to start off with and not having any calsses available to go to in order to teach me it. So far Ive been just trying to make a simple counter that would pulse an led every second, and so far no luck. Im getting errors left and right, when I change one thing, I get another error, and when I fix that I seem to get others. ...


How do I use the DDS core in a verilog flow?

Started by xilinx_user in comp.arch.fpga15 years ago 14 replies

I am new to using Xilinx cores. My intention is to use the DDS core, for which I was able to generate a number of files using coregen....

I am new to using Xilinx cores. My intention is to use the DDS core, for which I was able to generate a number of files using coregen. It appears that only the "padded" EDIF can be run through the backend stages. My question - as naive as it is - is what do you instantiate in a higher level verilog module in order to implement the design?


verilog versus vhdl

Started by Markus Zingg in comp.arch.fpga15 years ago 48 replies

Hi Group I have to implement a design which requires an FPGA, but to do so among other things I obviousely first have to learn one of the...

Hi Group I have to implement a design which requires an FPGA, but to do so among other things I obviousely first have to learn one of the two mentioned languages. I got the impression that europe seems to be more vhdl centric whereas verilog seems to be more popular in the US but this argument alone is for reasons beond the scope of this question not so important to me. I have a strong bac...


Re: Topics and Ideas for BS Project

Started by Evan Lavelle in comp.arch.fpga14 years ago 1 reply

I'm afraid that you are, and I'm trying to be polite here, completely wrong. SystemC does not operate the way that you think it does,...

I'm afraid that you are, and I'm trying to be polite here, completely wrong. SystemC does not operate the way that you think it does, and neither do VHDL nor Verilog. All three define simulation semantics in what is fundamentally exactly the same way. Some simple Googling might convince you. Look up any thread that discusses an endless loop which hangs up a Verilog or VHDL simulator. How i...


Design Notation VHDL or Verilog?

Started by vsh in comp.arch.fpga9 years ago 35 replies

any comments on either VHDL or Verilog?

any comments on either VHDL or Verilog?


Debounce in Verilog?

Started by eromlignod in comp.arch.fpga13 years ago 4 replies

Hi guys: I'm using a Xilinx FPGA for an application and I'm having trouble with an input square wave that has a little bounce at its...

Hi guys: I'm using a Xilinx FPGA for an application and I'm having trouble with an input square wave that has a little bounce at its transitions. At this stage of the game, it would be difficult for me to eliminate the bounce at the source. Is there an easy way to do a software debounce in Verilog? Thanks. Don


Verilog Book Recommendation

Started by Al Clark in comp.arch.fpga17 years ago 7 replies

I want to learn Verilog for small FPGA degigns. I don't have a background in VHDL but I am an experienced designer. For simple designs, I have...

I want to learn Verilog for small FPGA degigns. I don't have a background in VHDL but I am an experienced designer. For simple designs, I have used the schematic capture method. What do you guys recommend? -- Al Clark Danville Signal Processing, Inc. -------------------------------------------------------------------- Purveyors of Fine DSP Hardware and other Cool Stuff Availabl...


Convert Schematic Files (.sch) to Verilog Files (.v) for simulation in ModelSim

Started by crai...@googlemail.com in comp.arch.fpga14 years ago 7 replies

Is there a way to convert a schematic file (.sch) into a functional verilog module (.v/.vf) from the command line? I want to do this so I can...

Is there a way to convert a schematic file (.sch) into a functional verilog module (.v/.vf) from the command line? I want to do this so I can compile the resulting verilog file with modelsim for simulation. I know how to do this from the ISE GUI, but it would be much easier if I could do it from the command line. Please bear in mind that I am using Xilinx ISE 9.1i or ModelSim XE III/ Start...


FPGA and Verilog question

Started by Anonymous in comp.arch.fpga16 years ago

Hello! I am very new to news groups, sorry if I'm doing something wrong. Couldn't you give me some useful links or something other, where I...

Hello! I am very new to news groups, sorry if I'm doing something wrong. Couldn't you give me some useful links or something other, where I can read about FPGA and FPGA programmators. I need to build FPGA programmator with Vetilog, but not familiar with Verilog nor FPGA (I program on C and other languages). Please help me


Newbie to FPGA

Started by anand in comp.arch.fpga15 years ago 12 replies

Hi, I am a pre-si verification engineer looking to learn HW design, synthesis and P&R through FPGAs. (I am already very comfortable...

Hi, I am a pre-si verification engineer looking to learn HW design, synthesis and P&R through FPGAs. (I am already very comfortable with Verilog, so that is not the issue, I really want to learn to "design+synthesize+P&R" as opposed to "code in verilog"). Recently checked out Spartan dev kit, looks very affordable. Questions: Is this the best way to go (for a hobbyist)? I am willing ...


Which to learn: Verilog vs. VHDL?

Started by Michael in comp.arch.fpga13 years ago 48 replies

Howdy - I'm just beginning with FPGAs. I am using a Spartan 3E Starter Kit with Xilinx ISE. I am an electrical engineer by training and did some...

Howdy - I'm just beginning with FPGAs. I am using a Spartan 3E Starter Kit with Xilinx ISE. I am an electrical engineer by training and did some verilog in my collegiate days - but that was quite some time ago and it is all very fuzzy now. I have decided that as an EE I should be familiar with FPGAs - so I'm re-educating myself. With that said - which would be more useful to learn in the indu...


"Multi-source in Unit" Verilog synthesis woes

Started by NRClark in comp.arch.fpga13 years ago 2 replies

Hi everybody, I'm working on a hobbyist board I'm designing to do some audio DSP. I'm a little new to Verilog, although not to programming in...

Hi everybody, I'm working on a hobbyist board I'm designing to do some audio DSP. I'm a little new to Verilog, although not to programming in general. So far the FPGA design work has been going smoothly enough, but I'm having some trouble with synthesizing the code I wrote for my DAC. I tried to avoid all of the 'common' mistakes and design for synthesizability, but there's some I must h...


Please Help:Modelsim-Altera License "Verilog Computer Based training course"

Started by Anonymous in comp.arch.fpga16 years ago

Hello, I bought this book "Verilog Computer-Based Training Course" CD-ROM and was trying to install Modelsim-Altera 5.5b. Exemplar...

Hello, I bought this book "Verilog Computer-Based Training Course" CD-ROM and was trying to install Modelsim-Altera 5.5b. Exemplar LeonardoSpectrum and Quartus II 1.1 web edition tools that came with this book. The book description says the tools has 1 year licensing for modelsim and leonardo spectrum. Here is the link to book description. http://www.ece.neu.edu/info/verilog/vcbtc/Act...


Mixed language design

Started by Anonymous in comp.arch.fpga14 years ago 8 replies

I have a simple design (about 300 logic elements / 150 registers) written in Verilog. It's highly self-contained (only about ten signals on the...

I have a simple design (about 300 logic elements / 150 registers) written in Verilog. It's highly self-contained (only about ten signals on the interface). (For the curious, it performs a function for analogue video). It's now proposed to incorporate this in a design which is otherwise VHDL (and over which I shall have no control). Obviously, the Verilog could be converted, but this w...


Verilog case statements

Started by rickman in comp.arch.fpga15 years ago 18 replies

While reviewing the code that the FPGA group has produced, I saw something that looks bad. It is not likely to affect the functionality, but it...

While reviewing the code that the FPGA group has produced, I saw something that looks bad. It is not likely to affect the functionality, but it is not good coding style and may use extra resources. They are using Verilog which is not my first HDL language and I am not as familiar with it as I am VHDL. But because the case statement is not fully specified the code below appears to me to p...


verilog multiplexer

Started by maxascent in comp.arch.fpga11 years ago 5 replies

I would like to create a generic multiplexer in Verilog were I can set the number of inputs and data bits. I can create something using 2...

I would like to create a generic multiplexer in Verilog were I can set the number of inputs and data bits. I can create something using 2 input multiplexers cascaded but this produces a priority structure which uses more logic resources. If anyone can give me a clue as to if it is possible that would be great. Jon --------------------------------------- This message was sent usin...


Verilog Newbie Question

Started by Kate Smith in comp.arch.fpga17 years ago 5 replies

The following code is my first Verilog program. It's running at 25MHz and that's what the counter is for. I'm trying to accomplish the same...

The following code is my first Verilog program. It's running at 25MHz and that's what the counter is for. I'm trying to accomplish the same thing by shifting bits instead of hard coding the output in case statements. I tried LED > 1 to no avail. Any comments and suggestions are appreciated! Thanks! Kate module ledbounce(clk, LED); input clk; output [3:0] LED; reg [19:0] cnt1


Modelling latches in Verilog

Started by Philip Pemberton in comp.arch.fpga16 years ago 2 replies

Hi, I'm trying to reimplement the design at in Verilog, targetting a Xilinx CPLD. Problem is, I've got all the GAL equations...

Hi, I'm trying to reimplement the design at in Verilog, targetting a Xilinx CPLD. Problem is, I've got all the GAL equations translated, but I can't work out how to handle the latches and buffers. Why am I doing this? Because I'm out of 74LS chips and all my suppliers are closed until Monday... Basically, when /LDW goe


More beginner's verilog questions

Started by Reza Naima in comp.arch.fpga15 years ago 43 replies

After I found out that I couldn't syntesize a lot of the verilog code ( http://awlnk.com/?aRts ), I had to redesign how I was going to implement...

After I found out that I couldn't syntesize a lot of the verilog code ( http://awlnk.com/?aRts ), I had to redesign how I was going to implement this design. I'm going for something significantly easier, though I'm breaking it up into more modular parts. I'm getting all sorts of errors from all over the place (using both silos synthesizer and the xilinx webpack). The code is very simple -...