Downsizing Verilog synthesization.

Started by eromlignod in comp.arch.fpga13 years ago 45 replies

Hi guys: I'm prototyping an application using a Xilinx Spartan-3 development board. I'm using this particular development kit because it is...

Hi guys: I'm prototyping an application using a Xilinx Spartan-3 development board. I'm using this particular development kit because it is suited to the large amount of I/O I need. I'm new to FPGA, so I have written the code in Verilog using almost exclusively a high-level, behavioural style. The program works, but synthesizes using 99% of the available slices. So if I try to change ...


Re: Anyone has the AMD flash AM29LV800B verilog model?

Started by Newhand in comp.arch.fpga17 years ago 2 replies

"Lost Temper" wrote in message news: ... > Hi > I can't find the verilog model for AM29LV800B in www.amd.com. > Please send me the...

"Lost Temper" wrote in message news: ... > Hi > I can't find the verilog model for AM29LV800B in www.amd.com. > Please send me the model. > Thanks and Regards Hi, man! You can ask AMD for it. I think it is free to use.


VHDL vs Verilog

Started by whygee in comp.arch.fpga11 years ago 38 replies

hi, recently I read a quote about VHDL vs Verilog, along the lines of "VHDL is made by SW people who don't understand HW and vice...

hi, recently I read a quote about VHDL vs Verilog, along the lines of "VHDL is made by SW people who don't understand HW and vice versa"... Does anybody know the exact wording and origin ? yg -- http://ygdes.com / http://yasep.org


Synthesize verilog code with Icarus for Spartan?

Started by Guenter Dannoritzer in comp.arch.fpga17 years ago 1 reply

Hello, I need to synthesize a verilog code for a Spartan device and was wondering whether I can use Icarus Verilog for this. I looked on...

Hello, I need to synthesize a verilog code for a Spartan device and was wondering whether I can use Icarus Verilog for this. I looked on the Icarus web page and it says that Icarus supports synthesis. I am pretty new to logic design and especially synthesis. Now I try to figure out how to synthesize my code for the Spartan. There are not really any device specific options given. The...


VGA signal generator using CPLD

Started by RF in comp.arch.fpga17 years ago 2 replies

Hello, I am new with CPLD and Verilog. I have made some code and posted on comp.lang.verilog but nobody responded. I need help. I don't...

Hello, I am new with CPLD and Verilog. I have made some code and posted on comp.lang.verilog but nobody responded. I need help. I don't know if this code works. I don't know how to make a test module. (I am using ISE Webpack 4.2 and MXE). Thanks. --- http://www.terra.es/personal9/listaco/VGAsignal.html (Project) Here goes: ====================================================...


Initialization of arrays in Verilog

Started by Till Wollenberg in comp.arch.fpga14 years ago 3 replies

Hi! Can anybody give me a hint on how to initialize an array of registers in Verilog with Xilinx ISE 7.1i? I tried the following code: |...

Hi! Can anybody give me a hint on how to initialize an array of registers in Verilog with Xilinx ISE 7.1i? I tried the following code: | reg [9:0] palette [3:0]; | // synthesis attribute INIT of palette is "40'b0000000011000000001101111101111101111000" XST accepts the code (== does not generate error messages or warnings), but seems to discard it later (currently I only read from the a...


system verilog

Started by mamtachalana in comp.arch.fpga17 years ago 1 reply

i want to use system verilog for system modelling,kindy tellme how can i use that and how can i write code suppose for example i want to make...

i want to use system verilog for system modelling,kindy tellme how can i use that and how can i write code suppose for example i want to make model of and gate with test benches how do i compile my code which compiler is required? tell me the whole details mamta


verilog 2 VHDL translator

Started by Quesito in comp.arch.fpga15 years ago 3 replies

Hi all, I'm looking for a verilog to VHDL translator. Does anybody can point me for a free tool please? thanks in advance, Francesco

Hi all, I'm looking for a verilog to VHDL translator. Does anybody can point me for a free tool please? thanks in advance, Francesco


Comment on my code style

Started by Chris Carlen in comp.arch.fpga17 years ago 5 replies

Greetings: I am learning Verilog from the book "A Verilog Primer 2nd. ed." by J. Bhasker. Here's my crack at a digital one shot. It works...

Greetings: I am learning Verilog from the book "A Verilog Primer 2nd. ed." by J. Bhasker. Here's my crack at a digital one shot. It works fine, or course, since I have already used it in real hardware. But I am interested in pointers on coding style or any other comments people might like to make: Note: some of the delays and the initial statement are for making the functional s...


initializing a small array in Verilog

Started by David Bridgham in comp.arch.fpga2 years ago 3 replies

In my Verilog code I have this line: reg [1:0] ip_list [0:3] = { 2'd2, 2'd1, 2'd0, 2'd1 }; Both Icarus and Vivado seem happy with it and...

In my Verilog code I have this line: reg [1:0] ip_list [0:3] = { 2'd2, 2'd1, 2'd0, 2'd1 }; Both Icarus and Vivado seem happy with it and it does what I expect. However, I recently discovered Verilator and its lint capability so I've been running it over all my code to see if there is anything I ought to clean up. Verilator does not like this code, it says the LHS only has 2 bits wh...


Two Verilog FSM style compare

Started by Davy in comp.arch.fpga16 years ago 9 replies

Hi all, There is a problem on How to write FSM in Verilog(http://www.asic-world.com/tidbits/verilog_fsm.html). Most synthesis tools recommend...

Hi all, There is a problem on How to write FSM in Verilog(http://www.asic-world.com/tidbits/verilog_fsm.html). Most synthesis tools recommend second "Using Two Always Blocks" style. But I would like to use third "Single Always" style. It seems more compact. What's the pros and cons between the two styles? I see that the third style may have state transition latency. But does the third s...


How do I instantiate an ADSU8 in ISE7.1i?

Started by Paul Marciano in comp.arch.fpga15 years ago 1 reply

Hi, I am trying to use the ADSU8 library element in ISE7.1i. The libraries guide says its inferred by HDL (Verilog in my case) but does not...

Hi, I am trying to use the ADSU8 library element in ISE7.1i. The libraries guide says its inferred by HDL (Verilog in my case) but does not give an example. I can create it with the schematic editor but not with Verilog. I have tried to express the unit in a number of different ways. Rather than embarrass myself by posting bad code, I'll just ask the question - is there a trick to i...


Help with Libero IDE and Verilog...

Started by Anonymous in comp.arch.fpga14 years ago 2 replies

Hi all, I recently purchased the Actel Fusion Starter Kit. I'm new to both Libero IDE and Verilog and was hoping for some guidance. All...

Hi all, I recently purchased the Actel Fusion Starter Kit. I'm new to both Libero IDE and Verilog and was hoping for some guidance. All I'm trying to do is turn LED D1 on when the voltage from the potentiometer exceeds 2 volts. This is as simple as you can get. So tell me if I'm wrong, but I think my system needs to include the following: * Analog System Builder * Flash Memory Syste...


Verilog Program With A Problem

Started by Bose in comp.arch.fpga18 years ago 1 reply

Hi to all, I'm writing a program using verilog at the moment. The program that i'm doing now is one of many blocks that will be finally linked...

Hi to all, I'm writing a program using verilog at the moment. The program that i'm doing now is one of many blocks that will be finally linked up together...Right now, i'm having some problems with my program...In my program, i have a part where i need to compare the input(eingated) & an output(eout_prev) of another program which is a D flip flop. So in my program what should i define "eou...


ISE: use verilog-modules in an vhdl-design-flow

Started by Thomas Oehme in comp.arch.fpga18 years ago 3 replies

Hallo, this may be an typical newbie-question(sorry). My project is described in vhdl, but i have an working component in verilog i want to...

Hallo, this may be an typical newbie-question(sorry). My project is described in vhdl, but i have an working component in verilog i want to use within. How will i get the component in my project ? thanks for any answer Thomas Oehme


could use some help with verilog/vhdl

Started by Dan K in comp.arch.fpga13 years ago 2 replies

I'm having a problem with a state machine written in verilog that I need to get into vhdl. My simulation license only allows vhdl and I can't...

I'm having a problem with a state machine written in verilog that I need to get into vhdl. My simulation license only allows vhdl and I can't afford one that will do both. The problems is worse because it simulates just fine, but fails Xilinx ppr. But it has also run Xilinx ppr, so I'm thinking it involves the work directory and "cleanup project files" too. Perhaps if I ppr using the...


What to look for when synthesising verilog code originally written for ASIC to FPGA?

Started by Anonymous in comp.arch.fpga14 years ago 1 reply

Regarding to necessary changes to verilog code, am I missing something, 1. caches and memories, replacing using FPGA block rams. 2. clock...

Regarding to necessary changes to verilog code, am I missing something, 1. caches and memories, replacing using FPGA block rams. 2. clock gating to clock enable 3. change latches to registers Anything else?


DDR* SDRAM modules for simulation

Started by Aleksandar Kuktin in comp.arch.fpga6 years ago 6 replies

Hi all. Is there, somewhere, an open-source Verilog (or VHDL, but Verilog is preferred) module of a DDR1/2/3 SDRAM that can be used for...

Hi all. Is there, somewhere, an open-source Verilog (or VHDL, but Verilog is preferred) module of a DDR1/2/3 SDRAM that can be used for simulating a memory chip/module?? I want to build a memory controller, but want to do as much as possible in the simulator and hopefully only verify the correctness of it in silicon.


State Machines.. and their efficiency.

Started by Anonymous in comp.arch.fpga16 years ago 3 replies

Hi all, I'm a low-level kind of programmer (and wannabe hardware designer). When I write a piece of code, be it assembly, C or Verilog, I...

Hi all, I'm a low-level kind of programmer (and wannabe hardware designer). When I write a piece of code, be it assembly, C or Verilog, I need to have a precise idea of how it will end up. I've began to explore the wonderful world of FPGAs and of the Verilog hardware description language, and while I do understand that combinational logic can be reduced to its minimum terms, and I also...


VGA display

Started by Abby in comp.arch.fpga18 years ago 9 replies

Hi! I' m working to a project a little difficult for me, 'cause for the first time I have to simulate a chess game using Fpga and verilog...

Hi! I' m working to a project a little difficult for me, 'cause for the first time I have to simulate a chess game using Fpga and verilog language. I need your advices! :-) Most of the project is realized. Final parts concern VGA display. I know I must work using HS and VS signals, but I don't know rightly how to simulate all that into verilog. I will be very happy if there's someone who c...